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參數(shù)資料
| 型號： | RIVA128 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | RIVA 128⑩ 128-BIT 3D MULTIMEDIA ACCELERATOR |
| 中文描述： | 麗娃128⑩128位3D多媒體加速器 |
| 文件頁數(shù)： | 36/85頁 |
| 文件大?。?/td> | 609K |
| 代理商： | RIVA128 |
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128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
36/85
Table 9.
Truth table of supported SGRAM commands
NOTES
1
2
3
FBCKE
is high and DSF is low for all supported commands.
Activates or deactivates
FBD[127:0]
during writes (zero clock delay) and reads (two-clock delay).
For
FBA9
low,
FBA10
determines which bank is precharged; for
FBA9
high, all banks are precharged irrespective of the
state of
FBA10
.
SDRAM/SGRAM Initialization
SDRAM/SGRAMs must be powered-up and initialized in a predefined manner. The first SDRAM/SGRAM
command is registered on the first clock edge following
PCIRST#
inactive.
All internal SDRAM/SGRAMbanks are precharged to bring the device(s) into the “all bank idle” state. The
SDRAM/SGRAM mode registers are then programmed and loaded to bring them into a defined state be-
fore performing any operational command.
SDRAM/SGRAM Mode register
The Moderegister defines the mode of operation ofthe SDRAM/SGRAM.This includes burst length, burst
type, read latency and SDRAM/SGRAM operating mode. The Mode register is programmed via the Load
Mode register and retains its state until reprogrammed or power-down.
Mode registerbits M[2:0] specifythe burst length; for the RIVA128ZXSDRAM/SGRAMinterface thesebits
are set to zero, selecting a burst length of one. In this case
FBA[7:0]
select the unique column to be ac-
cessed and Mode register bit M[3] is ignored. Mode register bits M[6:4] specify the read latency; for the
RIVA128ZX SDRAM/SGRAM interface these bits are set to either 2 or 3, selecting a burst length of 2 or
3 respectively.
Command
1
FBCS0#,
FBCS1#
FBRAS# FBCAS# FBWE#
FBDQM
FBA[10:0]
FBD[127:0] Notes
Command inhibit
(NOP)
H
x
x
x
x
x
x
No operation
(NOP)
L
H
H
H
x
x
x
Active
(select bank and
activate row)
L
L
H
H
x
FBA[10]
=bank
FBA[9:0]
=row
x
Read
(select bank and
column and start read
burst)
L
H
L
H
x
FBA[10]
=bank
FBA[9]
=0
FBA[7:0]
=col
x
Write
(select bank and
column and start write
burst)
L
H
L
L
x
FBA[10]
=bank
FBA[9]
=0
FBA[7:0]
=col
valid data
Precharge
(deactivate
row in bank or banks)
L
L
H
L
x
FBA[10]
=code
x
3
Load mode register
L
L
L
L
x
FBA[10:0] =
opcode
Write enable/output
enable
-
-
-
-
L
-
active
2
Write inhibit/output
High-Z
-
-
-
-
H
-
high-Z
2
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