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參數(shù)資料
| 型號： | RIVA128 |
| 廠商： | 意法半導體 |
| 英文描述： | RIVA 128⑩ 128-BIT 3D MULTIMEDIA ACCELERATOR |
| 中文描述： | 麗娃128⑩128位3D多媒體加速器 |
| 文件頁數(shù)： | 70/85頁 |
| 文件大?。?/td> | 609K |
| 代理商： | RIVA128 |
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128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
70/85
Byte offsets 0x07 - 0x04
Device Status Register (0x07 - 0x06)
0x07
0x06
0x05
0x04
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
S
R
R
R
D
R
6
C
R
R
S
R
P
W
R
B
M
I
Bits
Function
R W I
31
Reserved
R - 0
30
SERR_SIGNALLED is set whenever the RIVA128ZX asserts SERR#.
R W 0
29
RECEIVED_MASTER indicates that a master device’s transaction (except for
Special Cycle) was terminated with a master-abort. This bit is clearable (=1).
0=No abort
1=Master aborted
R W 0
28
RECEIVED_TARGET indicates that a master device’s transaction was termi-
nated with a target-abort. This bit is clearable (=1).
0=No abort
1=Master received target aborted
R W 0
27
Reserved
R - 0
26:25
The DEVSEL_TIMING bits indicate the timing of
DEVSEL#
. These bits indi-
cate the slowest time that the RIVA128ZX asserts
DEVSEL#
for any bus
command
except
Configuration
Read
RIVA128ZX responds with medium
DEVSEL#
for VGA, memory and I/O
accesses. For accesses to the 16MByte memory ranges described by the
BARs, the chip responds with fast decode (no wait states).
00=fast
01=medium
and
Configuration
Write. The
R - 1
24:22
Reserved
R - 0
21
66MHZ indicates that the RIVA128ZX is capable of 66MHz operation. This bit
reflects the latched state of the 66MHz/33MHz strap option.
R - 1
20
CAP_LIST indicates that there is a linked list of registers containing informa-
tion about new capabilities not available within the original PCI configuration
structure. This bit indicates that the (byte) Capability Pointer Register located
at 0x34 points to the start of this linked list.
The value of CAP_LIST depends on the RIVA128ZX power-on reset configu-
ration Host Interface and ACPI Supported settings:
0 = Host Interface is PCI and ACPI not supported
1= Host interface is AGP or ACPI supported
R - X
19:16
Reserved
R - 0
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