- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373274 > RIVA128ZX (意法半導(dǎo)體) 128-BIT 3D MULTIMEDIA ACCELERATOR PDF資料下載
參數(shù)資料
| 型號： | RIVA128ZX |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 128-BIT 3D MULTIMEDIA ACCELERATOR |
| 中文描述： | 128位3D多媒體加速器 |
| 文件頁數(shù)： | 17/85頁 |
| 文件大小： | 609K |
| 代理商： | RIVA128ZX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁
128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
17/85
Figure 5.
Basic AGP pipeline concept
Pipeline operation
Memory access pipelining provides the main per-
formance enhancement of AGP over PCI. AGP
pipelined bus transactions share most of the PCI
signal set, and are interleaved with PCI transac-
tions on the bus.
The RIVA128ZX supports AGP pipelined reads
with a 4-deep queue of outstanding read requests.
Pipelined
reads are
primarily
RIVA128ZX for cache filling, the cache size being
optimized for AGP bursts. Depending on the AGP
bridge, a bandwidth ofup to 248MByte/s is achiev-
able for 128-byte pipelined reads. This compares
with around 100MByte/s for 128-byte 33MHz PCI
reads. Another feature of AGP is that for smaller
sized reads the bandwidth is not significantly re-
duced. Whereas 16-byte reads on PCI transfer at
around 33MByte/s, on AGP around 175MByte/s is
achievable. The RIVA128ZX actually requests
reads greaterthan 64 bytes in multiples of 32-byte
transactions.
used
by
the
The pipedepth canbe maintained bythe AGP bus
master (RIVA128ZX) intervening in a pipelined
transfer to insert new requests between data re-
plies. This bus sequencing is illustrated in Figure
5.
When the bus is in an idle condition, the pipe can
be started by inserting one or more AGP access
requests consecutively. Once the data reply to
those accesses starts, that stream can be broken
(or intervened) bythe busmaster (RIVA128ZX) in-
serting one or more additional AGP access re-
quests or inserting a PCI transaction. This inter-
vention is accomplished with the bus ownership
signals,
PCIREQ#
and
PCIGNT#
.
The RIVA128ZX implements both high and low
priority reads depending of the status of the ren-
dering engine. If the pipeline is likely to stall due to
system memory read latency, a high priority read
request is posted.
Address Transactions
The RIVA128ZX requests permission from the
bridge to use
PCIAD[31:0]
to initiate either an
AGP request or a PCI transaction by asserting
PCIREQ#
. The arbiter grants permission by as-
serting
PCIGNT#
with
AGPST[2:0]
equal to ”111”
(referred to as START). When the RIVA128ZX re-
ceives START it must start the bus operation with-
in two clocks of the bus becoming available. For
example, when the busis in an idle condition when
START is received, the RIVA128ZX must initiate
the bus transaction on the next clock and the one
following.
Figure 6 shows a single address being enqueued
by the RIVA128ZX. Sometime before clock 1, the
RIVA128ZX asserts
PCIREQ#
to gain permission
to use
PCIAD[31:0]
. Thearbiter grantspermission
by indicating START on clock 2. A new request
(address, command and length) are enqueued on
each clock in which
AGPPIPE#
is asserted. The
address of the request to be enqueued is present-
ed on
PCIAD[31:3]
, the lengthon
PCIAD[2:0]
and
the command on
PCICBE[3:0]#
. In Figure 6 only
a single address is enqueued since
AGPPIPE#
is
just asserted for a single clock. The RIVA128ZX
indicates that the current address is the last it in-
tends to enqueue when
AGPPIPE#
is asserted
and
PCIREQ#
is deasserted (occurring on clock
3). Once the arbiter detects the assertion of
AGP-
PIPE#
or
PCIFRAME#
it deasserts
PCIGNT#
on
clock 4.
Bus Idle
Pipelined
data
transfer
Intervene
cycles
Pipelined AGP requests
A1
A2
Data-1
Data-2
A3
PCI transaction
A
Data
Data-3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RIVA128 | RIVA 128⑩ 128-BIT 3D MULTIMEDIA ACCELERATOR |
| RIX-0142-H | FILTER IEC EINGANG ULTRA KOMPAKT 1A |
| RIX-0342-H | FILTER IEC EINGANG ULTRA KOMPAKT 3A |
| RIX-0642-H | FILTER IEC EINGANG ULTRA KOMPAKT 6A |
| RJ45SRB-BLACK | TUELLE FUER RJ45 STECKER SW Inhalt pro Packung: 8 Stk. |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RIVCF256H | 制造商:STEC Inc 功能描述:256MB COMPACT FLASH - Bulk |
| RIVET DPG FLOAT MTG | 制造商:ITT Interconnect Solutions 功能描述:Rack & Panel |
| RIVET(SSR389) | 制造商: 功能描述: 制造商:undefined 功能描述: |
| RIVET-DPD-PIN-INSERT-SPCR | 制造商:ITT Interconnect Solutions 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。