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參數(shù)資料
| 型號(hào)： | RIVA128ZX |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 128-BIT 3D MULTIMEDIA ACCELERATOR |
| 中文描述： | 128位3D多媒體加速器 |
| 文件頁(yè)數(shù)： | 79/85頁(yè) |
| 文件大?。?/td> | 609K |
| 代理商： | RIVA128ZX |
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128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
79/85
Byte offset 0x3F - 0x3C
MAX_LAT Register (0x3F
)
MIN_GNT Register (0x3E)
Interrupt Pin Register (0x3D)
Interrupt Line Register (0x3C)
0x3F
0x3E
0x3D
0x3C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
M
M
I
I
Bits
Function
R W I
31:24
The MAX_LAT bits contain the maximum time the RIVA128ZX requires to
gain access to the PCI bus. This read-only register is used to specify the
RIVA128ZX’s desired settings for Latency Timer values. The value specifies a
period of time in units of 250ns.
1=250ns
R - 1
Bits
Function
R W I
23:16
The MIN_GNT bits contain the length of the burst period the RIVA128ZX
needs, assuming a clock rate of 33MHz. This read-only register is used to
specify the RIVA128ZX’s desired settings for Latency Timer values. The value
specifies a period of time in units of 250ns.
3=750ns
R - 3
Bits
Function
R W I
15:8
The INTERRUPT_PIN bits contain the interrupt pin the device (or device func-
tion) uses. A value of 1 corresponds to
INTA#
.
R - 1
Bits
Function
R W I
7:0
The INTERRUPT_LINE bits contain the interrupt routing information. POST
software will write the routing information into this register as it initializes and
configures the system. The value in this field indicates which input of the sys-
tem interrupt controller(s) the RIVA128ZX’s interrupt pin is connected to.
Device drivers and operating systems can use this information to determine
priority and vector information. INTERRUPT_LINE is initialized to 0xFF (no
connection) at reset.
0=Interrupt line IRQ0
1=Interrupt line IRQ1
0xF=Interrupt line IRQ15
0xFF=No interrupt line connection (reset value)
R W 0xFF
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