參數(shù)資料
型號(hào): RIVA128ZX
廠(chǎng)商: 意法半導(dǎo)體
英文描述: 128-BIT 3D MULTIMEDIA ACCELERATOR
中文描述: 128位3D多媒體加速器
文件頁(yè)數(shù): 72/85頁(yè)
文件大小: 609K
代理商: RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
72/85
Byte offsets 0x0B - 0x08
Class Code Register (0x0B - 0x09)
Revision Identification Register (0x08)
0x0B
0x0A
0x09
0x08
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
C
R
Bits
Function
R W I
31:8
The CLASS_CODE bits identify the generic function of the device and (in
some cases) a specific register-level programming interface. The register is
broken into three byte-size fields. The upper byte (at offset 0x0B) is a base
class code which broadly classifies the type of function the device performs.
The middle-byte (at offset 0x0A) is a sub-class code which identifies more
specifically the function ofthe device. The lowerbyte (at offset 0x09) identifies
a specific register-level programming interface (if any) so that device indepen-
dent software can interact with the device.
The VGA function responds as a VGA compatible controller.
0x030000=VGA compatible controller
R - X
Bits
Function
R W I
7:0
The REVISION_ID bits specify a device specific revision identifier. The value
is chosen by the vendor.This field should be viewed as a vendor defined
extension to the DEVICE_ID.
0x01=Revision B
R - X
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