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參數(shù)資料
| 型號(hào)： | RIVA128ZX |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 128-BIT 3D MULTIMEDIA ACCELERATOR |
| 中文描述： | 128位3D多媒體加速器 |
| 文件頁數(shù)： | 55/85頁 |
| 文件大?。?/td> | 609K |
| 代理商： | RIVA128ZX |
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128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
55/85
10
The RIVA128ZX latches its configuration on the
trailing edge of
RST#
and holds its system bus in-
terface ina high impedancestate until this time. To
accomplish this, pull-up or pull-down resistors are
connected to the
FBA[9:0]
pins as appropriate.
Since there are no internal pull-up or pull-down re-
sistors and the address busshould be floating dur-
ing reset, a resistor value of up to 47K
, but no
less than 10K
, should be sufficient.
The power-on reset configuration seen by the chip
may be overwritten.The external
FBA[9:0]
config-
uration is stored in latches. An additional writable
register, containing all of the configuration bits
POWER-ON RESET CONFIGURATION
plus an additional STRAP_OVERWRITE bit (reg-
ister bit [11]), exists in parallel with the latches to
allow the host to overwrite the externalvalue. Writ-
ing to address BOOT_0 (0x00101000) writes into
this register.
The STRAP_OVERWRITE bit controls whether
the latches or the parallel writable register are se-
lected. When STRAP_OVERWRITE is set to 0,
the latched
FBA[9:0]
configuration is selected.
When set to 1, the chip uses the register value.
Reading from address BOOT_0 reads either the
configuration latches or the parallel register de-
pending on the STRAP_OVERWRITE setting.
Power-on reset FBA[9:0] bit assignments
[9]
AGP Mode. This bit selects whether the AGP bus 1X or 2X mode is enabled.
0 = AGP 2X mode enabled
1 = AGP 1X mode enabled
TV Mode. These bits select the timing format when TV mode is enabled.
00 = Reserved
01 = NTSC
10 = PAL
11 = TV mode disabled
Crystal Frequency. This bit should match the frequency of the crystal or reference clock connect-
ed to
XTALOUT
and
XTALIN
.
0 = 13.500MHz (used where TV output may be enabled)
1 = 14.31818MHz
Host Interface
0 = PCI
1 = AGP
RAM Width
0 = 64-bit framebuffer data bus width (the upper 64-bit data bus and byte selects are tri-state)
1 = 128-bit framebuffer data bus width
Although a 10K
resistor is used to strap the default state of this bit in RIVA 128 and RIVA128ZX
reference designs, it is ignored by the video BIOS which auto-detects the memory type and con-
figures the RIVA128ZX appropriately.
APCI Supported
0 = ACPI registers not supported. This provides compatibility with the PCI register configuration
as implemented by RIVA 128. The RIVA128ZX will be identified by DEVICE_ID_CHIP = 0x18 at
PCI Configuration offset 0x0.
1 = ACPI registers supported. Power management registers supported in PCI configuration
space. The RIVA128ZX will be identifiedby DEVICE_ID_CHIP= 0x19 at PCI Configuration offset
0x0.
[8:7]
[6]
[5]
[4]
[3]
9
8
7
6
5
4
3
2
1
0
AGP
Mode
TV Mode
Crystal
Host
Interface
RAM
Width
ACPI
Sup-
ported
RAM
Type
Sub-
Vendor
Bus
Speed
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