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參數(shù)資料
| 型號： | SAA4979H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Sample rate converter with embedded high quality dynamic noise reduction and expansion port |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | 28 X 28 X 3.40 MM, PLASTIC, QFP-128 |
| 文件頁數(shù)： | 14/52頁 |
| 文件大?。?/td> | 224K |
| 代理商： | SAA4979H |
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2002 May 28
14
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality
dynamic noise reduction and expansion port
SAA4979H
The detail-counter calculates the number of absolute
differences between current and previous pixels within a
programmable interval defined by the control inputs
lb_detail and upb_detail. The result of the 16-bit
detail-counter (control outputs: detail_cnt_h and
detail_cnt_l) can be used to increase or decrease the
result of the noise estimation figure (control input:
compensate).
In order to reduce the effect of clipping, only the blocks
where the sum of the luminance value is within a
predefined range are taken into account. The control
signal clip_offs can be used to increase or decrease this
range. A grey-counter gives information whether enough
pixels with values in the grey range are present in a video
field (control output: grey_cnt). When this number is lower
than a predefined threshold, e.g. for complete fields
towards black or white, all blocks are taken into account.
7.2
Embedded DRAM
7.2.1
3.5-M
BIT FIELD MEMORY
The basic functionality of the field memory, which is shown
in Fig.5, is similar to the SAA4956TJ. The memory size is
extended to 3538944 bits. The data path is 16-bit wide
(8-bitchrominanceand8-bitluminance).Thefieldmemory
is capable of storing, for example, up to 307 video lines of
720 pixels in a 4 : 2 : 2 format. After writing or reading
18 words of 16-bit width, a data transfer is performed from
the serial to parallel data registers (writing) or from the
parallel to the serial registers (reading). The field memory
has one write interface (controller and registers) to store
1f
H
data and two read interfaces, one to read field delayed
1f
H
data for the noise reduction function and the other to
read 2f
H
data for the following data processing. Since two
asynchronous clock domains are involved (SWCKint as
1f
H
clock and SRCKint as 2f
H
clock) the read and write
access to the memory array is controlled asynchronously
by the memory arbitration logic triggered via request and
acknowledge pulses.
The write operation starts with a reset write (RSTWint)
address pointer operation during the write enable (WEint)
LOW phase. The RSTWint LOW-to-HIGH transition,
referred to the rising edge of the write clock SWCKint,
must be at least 18 clock cycles ahead of the first written
data (WEint HIGH) and 18 clock cycles after the last
written data. The reset write transfers data temporarily
stored in the serial write registers to the memory array and
resets the write counter to the lowest address. Write
enable (WEint) is used to enable or disable a data write
operation. The WEint signal controls the data inputs
D0 to D15.
In addition, the internal write address pointer is
incremented if WEint is HIGH at the positive transition of
the SWCKint write clock. The data is latched if WEint was
HIGH at the previous positive transition of SWCKint. Input
enable (IEint) LOW can also suppress the storage of the
data into the memory array but does not influence the write
pointer increment. It is used to freeze parts of the field data
e.g for PIP processing.
The read operation starts with a reset (RSTRint) of the
read address pointer during the read enable (REint) LOW
phase. The RSTRint LOW-to-HIGH transition, referred to
the rising edge of the read clock SRCKint, must be at least
18 clock cycles ahead of the first read data (REint HIGH)
and 18 clock cycles after the last read data. The reset read
resetsthereadcountertothelowestaddressandrequests
a read operation of the data of the lowest address to the
serial read register. Read enable (REint) is used to enable
or disable the read operation. The REint controls the data
outputs Q0 to Q15. REint HIGH increments the read
counter.
In parallel to the write operation a read2 operation is done
using the same control signals as the write operation:
SWCKint, WEint and RSTWint. It reads the old data of the
previous field. The data Qold is needed as data input
(Dfielddelay) for the noise reduction.
When the WEint signal is HIGH it indicates that active
video (valid 1f
H
data) is to be stored. The start of WEint
HIGH is triggered by the H and V status bits of the ITU
data stream. The start of WEint HIGH can be delayed by
the control signals weint_hstart (number of clock delays)
and weint_vstart (number of video lines delay). The stop of
WEint HIGH is controlled by weint_hstop and weint_vstop.
When the IEint signal is HIGH it indicates that active video
(valid 1f
H
data) is also to be stored. The video data is not
stored and earlier written data is maintained (frozen) if
WEint is HIGH and IEint is LOW. The start of IEint HIGH is
triggeredbytheH and VstatusbitsoftheITUdatastream.
The start of IEint HIGH can be delayed by the control
signals ieint_hstart (number of clock delays) and
ieint_vstart (number of video lines delay). The stop of IEint
HIGH is controlled by ieint_hstop and ieint_vstop.
RSTWint is triggered by the V status bit of the ITU data
stream.
RSTRint is identical to the VD output signal.
REint is provided by the following sample rate conversion
to gather 2f
H
data if it is needed.
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