參數(shù)資料
型號： SAA4979H
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： Sample rate converter with embedded high quality dynamic noise reduction and expansion port
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP128
封裝： 28 X 28 X 3.40 MM, PLASTIC, QFP-128
文件頁數(shù)： 25/52頁
文件大?。?/td> 224K
代理商： SAA4979H
2002 May 28
25
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality
dynamic noise reduction and expansion port
SAA4979H
Table 7
Write register at 2f
H
HOST
ADDRESS
(HEX)
BIT
NAME
DESCRIPTION
Host address 0222H to 023FH (system control)
0222
0223
0224
0225
0226
0 to 7
0 to 7
0 to 7
0 to 7
0 to 3
4 to 7
0 to 1
2 to 3
4 to 7
0 to 2
3 to 4
6 to 7
0 to 7
0 to 7
0
1
2
vd_vstart
vd_vstop
reo_vstart
reo_vstop
dspflds
reo_vstart (MSBs)
reo_vstop (MSBs)
vd_vstart (MSBs)
vd_vstop (MSBs)
ads_hstart
ads_hstop
vres_dis
crn_direct
dr_aabb
vertical deflection pulse start (lower 8 of 11 bits)
vertical deflection pulse stop (lower 8 of 11 bits)
read enable output window vertical start (lower 8 of 10 bits)
read enable output window vertical stop (lower 8 of 10 bits)
number of display fields minus 1
reserved
read enable output window vertical start (higher 2 of 10 bits)
read enable output window vertical stop (higher 2 of 10 bits)
reserved
vertical deflection pulse start (higher 3 of 11 bits)
vertical deflection pulse start (higher 3 of 11 bits)
reserved
auxiliary display signal horizontal start (lower 8 of 10 bits)
auxiliary display signal horizontal stop (lower 8 of 10 bits)
internal vertical reset; 0 = enable; 1 = disable
direct vertical frame synchronization; 0 = disable; 1 = enable
display raster mode; 0 = standard VD synchronization; 1 = AABB
synchronization; VD delayed for the first 50 Hz field
reserved
generator mode; 0 = off; 1 = on
input enable signal (output IE)
smooth lock synchronization mode; 0 = off; 1 = on
reserved
auxiliary display signal vertical start (lower 8 of 10 bits)
auxiliary display signal vertical stop (lower 8 of 10 bits)
auxiliary display signal horizontal start (higher 2 of 10 bits)
auxiliary display signal horizontal stop (higher 2 of 10 bits)
auxiliary display signal vertical start (higher 2 of 10 bits)
auxiliary display signal vertical stop (higher 2 of 10 bits)
horizontal deflection pulse start; 4 pixels resolution
horizontal deflection pulse stop; 4 pixels resolution
read enable output window horizontal start (lower 8 of 10 bits)
read enable output window horizontal stop (lower 8 of 10 bits)
read enable output window horizontal start (higher 2 of 10 bits)
read enable output window horizontal stop (higher 2 of 10 bits)
reserved
display field length (lower 8 of 11 bits)
0227
0228
0229
022A
022B
3
4
5
6
7
0 to 7
0 to 7
0 to 1
2 to 3
4 to 5
6 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 1
2 to 3
4 to 7
0 to 7
gen_mode
ie_fm2
smooth_lock
ads_vstart
ads_vstop
ads_hstart (MSBs)
ads_hstop (MSBs)
ads_vstart (MSBs)
ads_vstop (MSBs)
hd_hstart
hd_hstop
reo_hstart
reo_hstop
reo_hstart (MSBs)
reo_hstop (MSBs)
fl
022C
022D
022E
0230
0231
0234
0235
0238
023A
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