參數(shù)資料
型號(hào)： SAA4979H
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Sample rate converter with embedded high quality dynamic noise reduction and expansion port
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP128
封裝： 28 X 28 X 3.40 MM, PLASTIC, QFP-128
文件頁(yè)數(shù)： 16/52頁(yè)
文件大?。?/td> 224K
代理商： SAA4979H
2002 May 28
16
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality
dynamic noise reduction and expansion port
SAA4979H
7.3
Digital processing at 2f
H
level
7.3.1
S
AMPLE RATE CONVERSION
The sample rate conversion block is used to obtain
848 active pixels per line out of the original 720 pixels
according to the relation of the two sampling frequencies
(32 MHz and 27 MHz). The interpolation for phase
positions between the original samples is achieved with a
variable phase delay filter with 10 taps for luminance
signals and 6 taps for chrominance signals.
The conversion to a higher sample frequency of 32 MHz is
done to improve the motion estimation performance in
combination with external feature ICs, which can process
up to 848 pixels per line at a 32 MHz clock. Bypassing this
function keeps the original 720 pixels per line (control
input: bypass_FSRC).
7.3.2
E
XPANSION PORT
For a further extension of the system an expansion port is
available, which is applicable for either a 4 : 2 : 2 format or
a reduced 4 : 1 : 1 format for data input and output at a
32 MHz line-locked clock; see Table 3. However, the
internal data is processed in a 8-bit wide 4 : 2 : 2 format.
To generate the 4 : 1 : 1 format at the output the U and V
samples from the 4 : 2 : 2 data stream are filtered by a
low-pass filter, before being subsampled with a factor of 2
and formatted to 4 : 1 : 1 format. Bypassing this function
keeps the data in the 4 : 2 : 2 format.
An internal bandwidth detector is implemented to detect
whether the colour difference signals provide either the full
4 : 2 : 2 bandwidth or a reduced 4 : 1 : 1 bandwidth.
Therefore absolute differences between original data and
downsampled data are calculated and can be read out by
the microcontroller (control output: UV_bw_detect). Low
absolute differences indicate that the original data does
not contain the full 4 : 2 : 2 bandwidth. This information
can be used to switch the upsample and downsample filter
on or off (control inputs: bypass_upsampling and
bypass_downsampling). Bandwidth detection is done
within a programmable window (control inputs: bw_hstart,
bw_hstop and bw_vstart, bw_vstop).
In the event of a 4 : 1 : 1 format at the input an upconverter
to 4 : 2 : 2 is applied with a linear interpolation filter for
creation of the extra samples. These are combined with
the original samples from the 4 : 1 : 1 stream.
The first phase of the YUV data stream is available on the
output bus two clock cycles after the rising edge of the REI
input signal. The start position, when the first phase of the
YUV data stream arrives on the input bus, can be set via
the control register exp_hstart.
The luminance output signal is in 8-bit straight binary
format, whereas the chrominance output signals are in
twos complement format. The input data at the expansion
slot is expected in the same format. U and V input signals
are inverted if the corresponding control bit mid_uv_inv is
set.
Table 3
YUV formats
OUTPUT PIN
YO7
YO6
YO5
YO4
YO3
YO2
YO1
YO0
UVO7
UVO6
UVO5
UVO4
UVO3
UVO2
UVO1
UVO0
4 : 1 : 1 FORMAT
Y17
Y16
Y15
Y14
Y13
Y12
Y11
Y10
U05
U04
V05
V04
4 : 2 : 2 FORMAT
Y07
Y06
Y05
Y04
Y03
Y02
Y01
Y00
U07
U06
U05
U04
U03
U02
U01
U00
INPUT PIN
YI7
YI6
YI5
YI4
YI3
YI2
YI1
YI0
UVI7
UVI6
UVI5
UVI4
UVI3
UVI2
UVI1
UVI0
Y07
Y06
Y05
Y04
Y03
Y02
Y01
Y00
U07
U06
V07
V06
Y27
Y26
Y25
Y24
Y23
Y22
Y21
Y20
U03
U02
V03
V02
Y37
Y36
Y35
Y34
Y33
Y32
Y31
Y30
U01
U00
V01
V00
Y17
Y16
Y15
Y14
Y13
Y12
Y11
Y10
V07
V06
V05
V04
V03
V02
V01
V00
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