參數(shù)資料
型號(hào)： SD1210
廠(chǎng)商： Electronic Theatre Controls, Inc.
英文描述： Dual-Interface SXGA TFT LCD Display Controller
中文描述： 雙接口SXGA TFT液晶顯示控制器
文件頁(yè)數(shù)： 16/46頁(yè)
文件大?。?/td> 322K
代理商： SD1210
SmartASI C, I nc.
SD1210
a certain amount of time delay synchronization pulse based upon the width of the
PWM signal. A brief circuit diagram for the PWM is shown in Figure 3.
November, 1999
Revision B
SmartASIC Confidential
16
The PWM signal from the SD1210 is a periodical signal with a period that is 1023
times the period of the free-running clock connected to the pin “CLK_1M”. System
manufacturers may select any frequency for the free running clock. The default clock
frequency is 1MHz. System manufacturers also decide the unit delay for the external
delay circuit. The delay information is stored in the EEPROM. When the SD1210
wants to delay the synchronization pulse for N units of delay, it will output the PWM
with the high time equal to (N * the period of the free-running clock), and with low
time equal to (1023-N)* the period of the free-running clock. When N=1023, the
PWM signal stays high all the time, and when N=0, the PWM signal is always low.
Figure 3: SD1210 PWM circuitry block diagram
3.1.5.
Free Running Clock
As described in previous section, a free-running clock is needed for the SD1210. This
clock is used for many of the SD1210’s internal operations. PWM operation is one of
them. System manufacturers can select the frequency of the free-running clock, and
the default clock frequency is 1MHz. System manufacturers can use an oscillator to
generate the free-running clock, and feed that clock directly to the pin “CLK_1M”, or
use a crystal connecting to “CLK_1M” and “CLK_1M_O”.
3.2.
Buffer memory and read/write control block
The SD1210 uses internal buffer memory to store a portion of the input image for
image scaling and output synchronization. No external memory buffer is needed for
the SD1210. The write control logic ensures the input data are stored into the right
area of the buffer memory, and the read control logic is responsible to fetch the data
from the buffer memory from the correct area and at the correct timing sequence.
With the precise timing control of the write and read logic, the output image is
SD1210
PWM
Delay
Circuitry
Synchronization pulse
PLL
Ref_Clk
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