參數(shù)資料
型號: SD1210
廠商: Electronic Theatre Controls, Inc.
英文描述: Dual-Interface SXGA TFT LCD Display Controller
中文描述: 雙接口SXGA TFT液晶顯示控制器
文件頁數(shù): 27/46頁
文件大?。?/td> 322K
代理商: SD1210
SmartASI C, I nc.
SD1210
November, 1999
Revision B
SmartASIC Confidential
27
[7:0]
lower bound for 832x624
Mode 832x624
Sync Polarity
Res5 threshold
[10:8]
Res5 threshold
[7:0]
Mode 1024x768
Sync Polarity
Res6 threshold
[10:8]
Res6 threshold
[7:0]
Mode 1152x864
Sync Polarity
Res7 threshold
[10:8]
Res7 threshold
[7:0]
Mode 1152x870
Sync Polarity
Res8 threshold
[10:8]
Res8 threshold
[7:0]
Mode 1280x960
Sync Polarity
Res9 threshold
[10:8]
Res9 threshold
[7:0]
Mode 1280x1024
Sync Polarity
Res10 threshold
[10:8]
Res10 threshold
[7:0]
Reserve mode 1
Sync Polarity
Reserve mode 1
Res threshold [10:8]
Reserve mode 1
Res threshold [7:0]
Reserve mode 2
Sync Polarity
Reserve mode 2
Res threshold [10:8]
Reserve mode 2
Res threshold [7:0]
Reserve mode 3
Sync Polarity
Reserve mode 3
Res threshold [10:8]
2
20DH[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
20DH[2:0] Upper bound of the line number for 832x624 mode
3
8
20EH
Upper bound of the line number for 832x624 mode, and
lower bound for 1024x768
20FH[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
20FH[2:0] Upper bound of the line number for 1024x768 mode
2
3
8
210H
Upper bound of the line number for 1024x768 mode, and
lower bound for 1152x864
211H[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
211H[2:0] Upper bound of the line number for 1152x864 mode.
2
3
8
212H
Upper bound of the line number for 1152x864 mode, and
lower bound for 1152x870
213H[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
213H[2:0] Upper bound of the line number for 1152x870 mode.
2
3
8
214H
Upper bound of the line number for 1152x870 mode, and
lower bound for 1280x960.
215H[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
215H[2:0] Upper bound of the line number for 1280x960 mode.
2
3
8
216H
Upper bound of the line number for 1280x960 mode, and
lower bound for 1280x1024.
217H[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
217H[2:0] Upper bound of the line number for 1280x1024 mode.
2
3
8
218H
Upper bound of the line number for 1280x1024 mode.
2
219H[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
219H[2:0] Resolution threshold for reserve mode 1
3
8
21AH
Resolution threshold for reserve mode 1
2
21BH[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
21BH[2:0] Resolution threshold for reserve mode 2
3
8
21CH
Resolution threshold for reserve mode 2
2
21DH[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
21DH[2:0] Resolution threshold for reserve mode 3
3
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