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參數(shù)資料
| 型號： | SD1210 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Dual-Interface SXGA TFT LCD Display Controller |
| 中文描述： | 雙接口SXGA TFT液晶顯示控制器 |
| 文件頁數(shù)： | 38/46頁 |
| 文件大?。?/td> | 322K |
| 代理商： | SD1210 |
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SmartASI C, I nc.
SD1210
November, 1999
Revision B
SmartASIC Confidential
38
OSD B Weight
Advanced Processing
R Weight
Advanced Processing
G Weight
Advanced Processing
B Weight
Advanced Processing
R Value
Advanced Processing
G Value
Advanced Processing
B Value
Brightness
Adjustment
Pixel Comparison
Value
Status 2
8
8
RW
RW
3AH[7:0] Mixing Weight For OSD B. Default is 00H.
3BH[7:0] Weight For Advanced Post Processing R
default is 00H
3CH[7:0] Weight For Advanced Post Processing G
Default is 00H
3DH[7:0] Weight For Advanced Post Processing B
Default is 00H
3EH[7:0] Value For Advanced Post Processing R
Default is 00H
3FH[7:0] Value For Advanced Post Processing G
Default is 00H
40H[7:0] Value For Advanced Post Processing B
Default is 00H
41H[7:0] The
Adjust
Brightness. Default is 00H.
42H[7:0] The Value To Compare The Incoming Pixel Data.
Default is 00H.
43H[7:0] The Status Register 2
8
RW
8
RW
8
RW
8
RW
8
RW
8
RW
Amount
For
Reducing/Increasing
8
RW
8
R
Bit [1:0]: Result for comparing the selected incoming
pixel with “Pixel Comparison Value”:
0: invalid
1: incoming pixel > “Pixel Comparison Value”
2: incoming pixel = “Pixel Comparison Value”
3: incoming pixel < “Pixel Comparison Value”
Bit [2]: Status for brightness control
0: Normal, no underflow/overflow
1:
brightness
underflow/increased too much causes overflow
reduced
too
much
causes
Bit [7:3]: Reserved
Clock Recovery Control Register:
Default value is 71H
Bit 0: clock frequency is divisible by 2
Bit 1: clock frequency is divisible by 4
Bit 2: clock frequency is divisible by 8
Bit 3: enable phase tracking feature
Bit 4: enable auto phase calibration
Bit 5: enable auto frequency calibration
Bit 6: enable auto mode detection
Bit 7: enable operation at half clock speed
Offset value added to the calibrated phase when phase
tracking occurs
Number of frames waited before phase tracking occurs
Recovery Control
8
RW
44H
Phase Range
4
RW
45H
Phase Track
Waiting Time
Quick Phase
Enable
PWM Enable
24
RW
46H
48H
49H[0]
1
RW
0: Normal phase calibration (default)
1: Final phase = phase total – phase offset
0: Disable auto phase total calculation
1: Enable auto phase total calculation (default)
0: Uses the external incoming SYNC signals
(default)
1: Allow the use of the default SYNC signals
instead of the incoming SYNC signals
1
RW
49H[1]
Standalone Enable
1
RW
49H[2]
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