參數(shù)資料
型號: SD1210
廠商: Electronic Theatre Controls, Inc.
英文描述: Dual-Interface SXGA TFT LCD Display Controller
中文描述: 雙接口SXGA TFT液晶顯示控制器
文件頁數(shù): 26/46頁
文件大小: 322K
代理商: SD1210
SmartASI C, I nc.
SD1210
November, 1999
Revision B
SmartASIC Confidential
26
Bit2: 0: single pixel input
1: dual pixel input
Bit3: 0: disable digital input
1: enable digital input
Bit4: 0: YUV input format is unsigned (128 offset)
1: YUV input format is signed
Bit5: 0: RGB input for video mode
1: YUV input for video mode
Bit6: 0: disable video input
1: enable video input
Bit7: 0: disable decimation support
1: enable decimation
Bit 0: 0: don’t invert input odd/even field indicator
1: invert input odd/even field indicator
Bit 1: 0: disable half clock mode for dual pixel input
1: enable half clock mode for dual pixel input
Bit 2: 0: disable BY2 for auto calibration
1: enable BY 2 for auto calibration
Bit 3: 0: disable BY4 for auto calibration
1: enable BY 4 for auto calibration
Bit 4: 0: disable BY8 for auto calibration
1: enable BY 8 for auto calibration
Bit7-5: output clock phase adjustment, larger number
gives larger phase delay.
Control byte 2
8
202H
Mode 640x350
Sync Polarity
Res0 threshold
[10:8]
Res0 threshold
2
203H[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
203H[2:0] Upper bound of the line number for 640x350 mode
3
[7:0]
8
204H
Upper bound of the line number for 640x350 mode, and
lower bound for 640x400
205H[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
205H[2:0] Upper bound of the line number for 640x400 mode
Mode 640x400
Sync Polarity
Res1 threshold
[10:8]
Res1 threshold
[7:0]
Mode 720x400
Sync Polarity
Res2 threshold
[10:8]
Res2 threshold
[7:0]
Mode 640x480
Sync Polarity
Res3 threshold
[10:8]
Res3 threshold
[7:0]
Mode 800x600
Sync Polarity
Res4 threshold
[10:8]
Res4 threshold
2
3
8
206H
Upper bound of the line number for 640x400 mode, and
lower bound for 720x400
207H[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
207H[2:0] Upper bound of the line number for 720x400 mode
2
3
8
208H
Upper bound of the line number for 720x400 mode, and
lower bound for 640x480
209H[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
209H[2:0] Upper bound of the line number for 640x480 mode
2
3
8
20AH
Upper bound of the line number for 640x480 mode, and
lower bound for 800x600
20BH[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
20BH[2:0] Upper bound of the line number for 800x600 mode
2
3
8
20CH
Upper bound of the line number for 800x600 mode, and
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