參數(shù)資料
型號(hào): SD1210
廠商: Electronic Theatre Controls, Inc.
英文描述: Dual-Interface SXGA TFT LCD Display Controller
中文描述: 雙接口SXGA TFT液晶顯示控制器
文件頁(yè)數(shù): 29/46頁(yè)
文件大?。?/td> 322K
代理商: SD1210
SmartASI C, I nc.
SD1210
November, 1999
Revision B
SmartASIC Confidential
29
it results in normal calibration time
(recommended)
3: when input video signal has no overshot,
it results in shortest calibration time
25AH-25BH The unit delay used in the external PWM delay circuitry.
If the free-running clock is 1MHz, and the intended unit
delay is 0.2 ns (= 5,000MHz), then a value of
5,000MHz/1MHz = 5,000 is used here.
25CH-25EH Maximum time when input VSYNC is off before the
LINK_DWN pin turns ON (unit: clock period of the free
running clock). If the free-running clock is 1MHz, and the
intended maximum time is 1 second, then a value of
1,000,000
μ
s/ 1
μ
s = 1,000,000 is used here.
25FH-260H Maximum refresh rate supported by the LCD panel.
If the intended maximum refresh rate is 75Hz, and the
free-running clock is 1MHz, then a value of
1000000/75=133,333 is used here
261H
Maximum source clock rate supported by the SD1010
(unit: frequency of free-running clock).
If the intended maximum clock rate is 60MHz, and the
free-running clock is 1MHz, then a value of 60 is used
here.
If the input signal has a higher frequency than this value,
the VCLK0_X status bit will turn ON.
262H-263H Minimum number of pixels per line for LCD panel
PWM unit delay
16
Maximum link off time
22
Maximum refresh rate
16
Maximum input
frequency
8
Minimum pixels per line
for LCD
LCD polarity
11
4
264H[3:0]
Controls the polarity of output VSYNC,
HSYNC, clock and display enable:
Bit0: 0: clock
active high, 1: clock active low
Bit1: 0: HSYNC active low, 1: HSYNC active high
Bit2: 0: VSYNC active low, 1: VSYNC active high
Bit4: 0: de active high, 1: de active low
265H[3]
Enable for programmable output pad:
1: output is enabled
0: output is tri-state
Output enable for output
pin 51-54, 56-59, 61-64,
66-69, 71-74, 76-79, 81-
84, 86-89, 91-97, 99,
101-104, 106-109
Driving
control for output pin
51-54, 56-59, 61-64, 66-
69, 71-74, 76-79, 81-84,
86-89, 91-97, 99, 101-
104, 106-109
1
capability
3
265H[2:0] 0: 2mA
1: 6mA
2: 6mA
3: 10mA
4: 4mA
5: 8mA
6: 8mA
7: 12mA
Enable for programmable output pad:
1: output is enabled
0: output is tri-state
266H[6:4] 0: 2mA
1: 6mA
2: 6mA
3: 10mA
4: 4mA
5: 8mA
Output enable for output
pin 49 (DE)
1
266H[7]
Driving
control for output pin 49
(DE)
capability
3
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