參數(shù)資料
型號: SDA9255
廠商: SIEMENS AG
英文描述: SRC-Scan Rate Converter SDA9255
中文描述: 鋼骨混凝土掃描頻率轉(zhuǎn)換器SDA9255
文件頁數(shù): 12/45頁
文件大小: 225K
代理商: SDA9255
SDA 9255
Semiconductor Group
10
1998-02-01
2.2
Output Data Formats
X
AB
:
X: signal component,
A: sample number,
B: bit number
2.3
The SDA 9255 has five input signals:
Input Timing and Parameter
The SDA 9255 includes a V-Sync delay block.This is implemented to make sure that the
field identification is working correctly. This is briefly described below.
The phase relation of the incoming horizontal synchronization signal (HIN) and the
incoming data for HSINP = 0 and VSINP = 0 is shown in figure 7 (
see chapter 5.1, Input
Timing of the SDA 9255 (HSINP = 0)
). The SDA 9255 needs the synchronization
enable input (SYNCEN) which is used to gate HIN and VIN. This is implemented for
frontends which are working with 13.5 MHz and a large output delay time for H-Sync and
Data
Pin
YOUT7
YOUT6
YOUT5
YOUT4
YOUT3
YOUT2
YOUT1
YOUT0
UVOUT7
UVOUT6
UVOUT5
UVOUT4
Y
07
Y
06
Y
05
Y
04
Y
03
Y
02
Y
01
Y
00
U
07
U
06
V
07
V
06
Y
17
Y
16
Y
15
Y
14
Y
13
Y
12
Y
11
Y
10
U
05
U
04
V
05
V
04
Y
27
Y
26
Y
25
Y
24
Y
23
Y
22
Y
21
Y
20
U
03
U
02
V
03
V
02
Y
37
Y
36
Y
35
Y
34
Y
33
Y
32
Y
31
Y
30
U
01
U
00
V
01
V
00
HIN
Pin 23
Horizontal synchronization signal - low
or high active
Vertical synchronization signal - low or
high active
Enable signal for HIN and VIN signal,
low active
Luminance input
Chrominance input
VIN
Pin 22
SYNCEN
Pin 30
YIN0 ... 7
UVIN4 ... 7 Pin 36, 37, 38, 39
Pin 42, 43, 44, 45, 46, 47 ,48, 49
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