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參數(shù)資料
| 型號(hào)： | SDA9255 |
| 廠(chǎng)商： | SIEMENS AG |
| 英文描述： | SRC-Scan Rate Converter SDA9255 |
| 中文描述： | 鋼骨混凝土掃描頻率轉(zhuǎn)換器SDA9255 |
| 文件頁(yè)數(shù)： | 26/45頁(yè) |
| 文件大小： | 225K |
| 代理商： | SDA9255 |
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SDA 9255
Semiconductor Group
24
1998-02-01
SYNC_ST (every 40 ms) are indicated with S“. The
Ι
2
C-Bus status bits of the SDA 9255
(sub19
H
, Bit 7; sub1E
H
, Bit 7) reflect the state of the register values. If these bits are read
as ’0’ then the store command was sent, but the data aren’t made available yet. If these
bits are ’1’ then the data were made valid and a new write or read cycle can start. The
I
2
C-Bus status bits have to be checked before writing or reading new data, otherwise
data can be lost by overwriting.
After switching on the IC, all bits of the SDA 9255 are set to defined states. In particular:
R/W:
Take over:
R-Read Register,
V-take over with V-Sync,
W-Write Register,
S-take over with SYNC_ST
R/W-Read and Write Register,
Subaddress Default
Value
6F
H
56
H
68
H
23
H
10
H
30
H
50
H
not used
61
H
74
H
8F
H
94
H
R/W
Take
Over
S
S
V
V
V
V
V
Subaddress Default
Value
A2
H
50
H
2C
H
81
H
00
H
not used
R/W
Take
Over
V
S
S
S
S
00
H
01
H
02
H
03
H
04
H
05
H
06
H
07
H
08
H
09
H
0A
H
0B
H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0C
H
0D
H
0E
H
0F
H
10
H
11
H
... 18
H
19
H
1A
H
... 1D
H
1E
H
1F
H
... FE
H
FF
H
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R
R/W
W
not used
V
V
V
V
not used
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