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參數(shù)資料
| 型號： | SDA9255 |
| 廠商： | SIEMENS AG |
| 英文描述： | SRC-Scan Rate Converter SDA9255 |
| 中文描述： | 鋼骨混凝土掃描頻率轉換器SDA9255 |
| 文件頁數(shù)： | 25/45頁 |
| 文件大?。?/td> | 225K |
| 代理商： | SDA9255 |
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SDA 9255
Semiconductor Group
23
1998-02-01
ZOOM:
PAN:
In the fourth column of table 5 the panning range is shown for NoOPL = 288.
If the pan factor is larger than specified in the previous equation, the last input line is used
for interpolation of the remaining lines. On the screen the last line is repeated.
Register value (0 ... 16)
Register value (0 ... 63)
2.7
I
2
C Bus
2.7.1
I
2
C-Bus Slave Address
2.7.2
I
2
C-Bus Format
The SDA 9255
I
2
C-Bus interface acts as a slave receiver and a slave transmitter and
provides three different access modes (write, read, continuous read). All modes run with
a subaddress auto increment. The interface supports the normal 100 kHz transmission
speed as well as the high speed 400 kHz transmission.
Write:
S:
A:
P:
NA:
Read:
Start condition
Acknowledge
Stop condition
Not Acknowledge
Continuous Read:
The transmitted data are internally stored in registers. The master has to write a don’t
care byte to the subaddress FF
H
(store command) to make the register values available
for the SDA 9255. To have a defined time step, where the data will be available, the data
are made valid with the incoming V-Sync or with the next SYNC_ST pulse, which is an
internal signal and indicates the start of a new output cycle of either four fields in 100/
120 Hz interlaced mode or two frames in 50/60 Hz proscan mode. The subaddresses,
where the data are made valid with the V-Sync (every 20 ms) are indicated in the
overview of the subaddresses with V“, where the data are made valid with the
1
0
1
1
1
1
0
S
1
0
1
1
1
1
0
0 A
Subaddress
A
Data Byte
A
*****
A P
S 1 0 1 1 1 1 0 0 A Subaddress A S 1 0 1 1 1 1 0 1 A Data Byte A
*****
Data Byte
NA
P
S
1
0
1
1
1
1
0
1
A
Data Byte
A
*****
Data Byte
NA P
Write Address: BC
H
Read Address: BD
H
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