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參數(shù)資料
| 型號： | SDA9255 |
| 廠商： | SIEMENS AG |
| 英文描述： | SRC-Scan Rate Converter SDA9255 |
| 中文描述： | 鋼骨混凝土掃描頻率轉(zhuǎn)換器SDA9255 |
| 文件頁數(shù)： | 15/45頁 |
| 文件大?。?/td> | 225K |
| 代理商： | SDA9255 |
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SDA 9255
Semiconductor Group
13
1998-02-01
2.3.4
In the SDA 9255 an H-Sync delay circuit is implemented. The output of this block is the
HS_int. The distance of the incoming H-Sync (HIN, falling edge for HSINP = 0) and the
active data is adjustable by the HSDLY register value and the MCNAPIP register value
(subaddress 0B
H
and 0C
H
,
see description of
I
2
C Bus
). With the HSDLY register the
delay of the external (HIN) to the internal H-Sync (HS_int) is adjustable.
Not Active Pixels of Input Field
DELAY (HIN to HS_int) = (HSDLY
*
64 + 4)
*
T
LL2CLK
This internal H-Sync (HS_int) is fed to the memory control unit. The MCNAPIP (memory
controller not active pixel at input) is used to adjust the distance to the active line in steps
of one system clock period. So the MCNAPIP is used to set the phase of the internal
generated clocks LL_CLK, LH_CLK and LQ_CLK.
DELAY (HS_int to active data) = (MCNAPIP + 61)
*
T
LL2CLK
The total distance of the falling edge of the incoming H-Sync (HIN, falling edge for
HSINP = 0) to the active data of the line is:
DELAY (HIN to active data) = (HSDLY
*
64 + MCNAPIP + 65)
*
T
LL2CLK
In the formula above you can see that the first active pixel occurs 65 system clocks after
the falling edge of the HIN signal, if HSDLY and MCNAPIP are set to zero.
In the figure 7 (
see chapter 5.1, Input Timing of the SDA 9255 (HSINP = 0)
) the input
timing of the SDA 9255 is shown. The luminance and chrominance data are coming with
half the system clock speed (e.g. 13.5 MHz). The SDA 9255 accepts the YIN data every
second edge of the LL2CLK clock; in the SDA 9255 the luminance and chrominance
data are sampled with the rising edge of the internal LL_CLK, which is half the system
clock (e.g. 13.5 MHz). At the position of the first active pixel the phase of the half system
clock (LL_CLK = 13.5 MHz), the quarter system clock (LH_CLK = 6.75 MHz) and the
eighth system clock (LH_CLK = 3.375 MHz) is always as shown in the diagram. The
LL_CLK is used for sampling the incoming data. The LQ_CLK is used to synchronize the
4:1:1 data stream.
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