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參數(shù)資料
| 型號： | SDA9255 |
| 廠商： | SIEMENS AG |
| 英文描述： | SRC-Scan Rate Converter SDA9255 |
| 中文描述： | 鋼骨混凝土掃描頻率轉換器SDA9255 |
| 文件頁數(shù)： | 28/45頁 |
| 文件大?。?/td> | 225K |
| 代理商： | SDA9255 |
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SDA 9255
Semiconductor Group
26
1998-02-01
2.7.4
Detailed Description
Subaddress 00
H
Bit
D7
Name
MODE10050
Function
Output mode switch:
0:
100/120 Hz (default value)
1:
50/60 Hz
1:
Should be set to 1
1:
Should be set to 1
Still picture:
0:
Off (default value)
1:
On
Chrominance input format:
0:
Unsigned input (0 ... 255)
1:
2’s complement input (-128 ... 127) (default value)
Inside the SDA 9255 the data are always processed as
unsigned data
Chrominance output format:
0:
Unsigned output (0 ... 255)
1:
2’s complement output (-128 ... 127) (default
value)
Television system:
00:
NTSC (1716)
01:
Automatic PAL (n
*
32)
10:
Automatic NTSC (n
*
32 + 20)
11:
PAL (1728) (default value)
The SDA 9255 is designed for a line-locked system.
Therefore the number of system clock periods between two
H-Sync (HIN) must be constant. In PAL (1728) mode the
number of system clocks (~27.0 MHz) per input line is
assumed to be constant 1728. In case of NTSC (1716)
mode the number of system clock periods is assumed to be
constant 1716. In automatic mode (01 and 10) the number
of system clock periods (~27.0 MHz) per incoming line is
measured and used to calculate the outgoing line length. In
automatic PAL mode the number of system clock periods
between two H-Syncs must be n
*
32 (n = 1, 2, ..., 54, ...).
In automatic NTSC mode the number of system clock
periods between two H-Syncs must be
n
*
32 + 20 (n = 1, 2, ..., 53, ...).
D6
D5
D4
FREEZE
D3
TWOIN
D2
TWOOUT
D1 ... D0 TVMODE
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