(V
參數(shù)資料
型號: SI5315-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 2/54頁
文件大?。?/td> 0K
描述: BOARD EVAL SI5315 8KHZ-644.53MHZ
應(yīng)用說明: SI5315/17 Crystal Selection AppNote
標準包裝: 1
主要目的: 計時,時鐘乘法器
嵌入式:
已用 IC / 零件: SI5315
主要屬性: 2 輸入,2 輸出
次要屬性: CML,CMOS,LVDS,LVPECL
已供物品: 板,CD,文檔
Si5315
10
Rev. 1.0
Figure 1. CKIN Voltage Characteristics
Figure 2. Rise/Fall Time Characteristics
Table 4. Jitter Generation
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 C)
Parameter
Symbol
Test Condition1,2,3,4
Min
Typ
Max
GR-253 Spec
Unit
Measuremen
t Filter (MHz)
DSPLL BW1
Jitter Gen OC-192
JGEN
0.02–80
167 Hz5
0.483
0.628
N/A
psrms
4–80
167 Hz5
0.302
0.392
N/A
psrms
0.05–80
167 Hz5
0.467
0.607
1.0 psrms
(0.01 UIrms
psrms
Jitter Gen OC-48
JGEN
0.012–20
167 Hz5
0.470
0.611
4.02 psrms
(0.01 UIrms)
psrms
111 Hz6
0.565
0.734
4.02 psrms
(0.01 UIrms)
psrms
IEEE 802.3 GbE
RMS Jitter
JGEN
1.875–20
83 Hz6
0.232
0.301
psrms
Notes:
1. BWSEL [1:0] loop bandwidth settings provided in Table 9 on page 20.
2. 40 MHz fundamental mode crystal used as XA/XB input.
3. VDD = 2.5 V
4. TA = 85 °C
5. Si5315A test condition: fIN = 19.44 MHz, fOUT = 156.25 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall time
(20–80%), LVPECL clock output.
6. Si5315B test condition: fIN =19.44 MHz, fOUT = 125 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall time (20-
80%), LVPECL clock output.
V
ISE , VOSE
V
ID,VOD
Differential I/Os
VICM, VOCM
Single-Ended
Peak-to-Peak Voltage
Differential
Peak-to-Peak Voltage
SIGNAL +
SIGNAL –
(SIGNAL +) – (SIGNAL –)
V
t
SIGNAL +
SIGNAL –
VID = (SIGNAL+) – (SIGNAL–)
V
ICM , VOCM
t
F
t
R
80%
20%
DOUT, CLOUT
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