參數(shù)資料
型號: SI5315-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 6/54頁
文件大?。?/td> 0K
描述: BOARD EVAL SI5315 8KHZ-644.53MHZ
應(yīng)用說明: SI5315/17 Crystal Selection AppNote
標準包裝: 1
主要目的: 計時,時鐘乘法器
嵌入式:
已用 IC / 零件: SI5315
主要屬性: 2 輸入,2 輸出
次要屬性: CML,CMOS,LVDS,LVPECL
已供物品: 板,CD,文檔
Si5315
14
Rev. 1.0
2. Typical Application Circuit
Figure 5. Si5315 Typical Application Circuit
Si5315
LOS1
LOS2
LOL
CKOUT1+
CKOUT1–
CKIN1 Loss of Signal Indicator
CKIN2 Loss of Signal Indicator
PLL Loss of Lock Indicator
CKOUT2+
CKOUT2–
2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).
CKIN1+
CKIN1–
Backplane or Line
Recovered Clock
Inputs
CKIN2+
CKIN2–
Notes:
3. Assumes manual input clock selection.
XA
XB
40 MHz Crystal
Option 1:
1. Assumes differential LVPECL termination (3.3 V) on clock inputs.
VD
D
GN
D
Ferrite
Bead
System
Power
Supply
C3
C2
C1
C4
0.1 F
1 F
130
130
82
82
VDD = 3.3 V
130
130
82
82
VDD = 3.3 V
Clock Outputs to
Ethernet PHYs
100
0.1 F
+
100
0.1 F
+
XA
XB
Ext. Refclk+
Option 2:
0.1 F
Ext. Refclk–
0.1 F
BWSEL[1:0]2
Bandwidth Select
VDD
15 k
15 k
SFOUT[1:0]2
Signal Format Select
VDD
15 k
15 k
DBL2_BY2
Clock Output 2 Disable/
Bypass Mode Control
VDD
15 k
15 k
FRQSEL[3:0]2
Frequency Select
VDD
15 k
15 k
FRQTBL2
Frequency Table Select
VDD
15 k
15 k
CS3
Input Clock Select
VDD
15 k
15 k
AUTOSEL2
Manual/Automatic Clock
Selection (L)
VDD
15 k
15 k
XTAL/Clock2
Crystal/Ref Clk
VDD
15 k
15 k
RST
Reset
G
ND
Pa
d
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