參數(shù)資料
型號: SI5315-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 30/54頁
文件大小: 0K
描述: BOARD EVAL SI5315 8KHZ-644.53MHZ
應(yīng)用說明: SI5315/17 Crystal Selection AppNote
標(biāo)準(zhǔn)包裝: 1
主要目的: 計時,時鐘乘法器
嵌入式:
已用 IC / 零件: SI5315
主要屬性: 2 輸入,2 輸出
次要屬性: CML,CMOS,LVDS,LVPECL
已供物品: 板,CD,文檔
Si5315
36
Rev. 1.0
6.2. Output Clock Drivers
The Si5315 has a flexible output driver structure that can drive a variety of loads, including LVPECL, LVDS, CML,
and CMOS formats. The signal format is selected for both CKOUT1 and CKOUT2 outputs using the SFOUT [1:0]
pins. This modifies the output common mode and differential signal swing. See Table 2, “DC Characteristics” for
output driver specifications. The SFOUT [1:0] pins are three-level input pins, with the states designated as L
(ground), M (VDD/2), and H (VDD). Table 17 shows the signal formats based on the supply voltage and the type of
load being driven.
Figure 15. Typical Differential Output Circuit
Figure 16. Typical CMOS Output Circuit (Tie CKOUTn+ and CKOUTn– Together)
For the CMOS setting (SFOUT = LH), both output pins drive single-ended in-phase signals. The CKOUT+/- can be
externally shorted together for greater drive strength specified in Table 2, “DC Characteristics”.
Table 17. Output Signal Format Selection (SFOUT)
SFOUT[1:0]
Signal Format
HL
CML
HM
LVDS
LH
CMOS
LM
Disabled
MH
LVPECL
ML
Low-swing LVDS
All Others
Reserved
Si5315
Rcvr
100
Z0 = 50
CKOUTn
CMOS
Logic
CKOUTn
Optionally Tie CKOUTn
Outputs Together for Greater Strength
Si5315
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