參數(shù)資料
型號: SI5315-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 31/54頁
文件大?。?/td> 0K
描述: BOARD EVAL SI5315 8KHZ-644.53MHZ
應(yīng)用說明: SI5315/17 Crystal Selection AppNote
標(biāo)準(zhǔn)包裝: 1
主要目的: 計時,時鐘乘法器
嵌入式:
已用 IC / 零件: SI5315
主要屬性: 2 輸入,2 輸出
次要屬性: CML,CMOS,LVDS,LVPECL
已供物品: 板,CD,文檔
Si5315
Rev. 1.0
37
Figure 17. Disable CKOUTn Structure
The SFOUT [1:0] pins can also be used to disable both outputs. Disabling the output puts the CKOUTn+ and
CKOUTn– pins in a high-impedance state relative to VDD (common mode tri-state) while the two outputs remain
connected to each other through a 200
on-chip resistance (differential impedance of 200 ). The maximum
amount of internal circuitry is powered down, minimizing power consumption and noise generation. Recovery from
the disable mode requires additional time as specified in Table 3, “AC Characteristics”.
SFOUT[1:0] = LM (Output Disable)
100
+
CKOUTn
Output from
DSPLL
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