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參數(shù)資料
| 型號(hào)： | SIS5595 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Pentium PCI System I/O Chipset |
| 中文描述： | 奔騰的PCI系統(tǒng)I / O芯片 |
| 文件頁(yè)數(shù)： | 15/216頁(yè) |
| 文件大?。?/td> | 2208K |
| 代理商： | SIS5595 |
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SiS5595 PCI System I/O Chipset
Preliminary V2.0 Nov. 2, 1998 9 Silicon Integrated Systems Corporation
3
FUNCTIONAL DESCRIPTION
SiS5595 is a highly integrated system I/O that constitutes a high performance, rich featured,
yet glueless solution for both Pentium and Pentium II systems.
The SiS5595 PCI system I/O integrates the PCI-to-ISA bridge with the DDMA and PC/PCI
DMA, Serial IRQ capability, the ACPI/Legacy PMU, the Data Acquisition Interface, the
Universal Serial Bus host/hub interface, and the ISA bus interface, which contains the ISA
bus controller, the DMA controllers, the interrupt controllers, and the Timers. It also
integrates the Keyboard controller, and the Real Time Clock (RTC). The built-in USB
controller, which is fully compliant to OHCI (Open Host Controller Interface), provides two
USB ports capable of running full/low speed USB devices. The Data Acquisition Interface
offers the ability of monitoring and reporting the environmental condition of the PC. It could
monitor 5 positive analog voltage inputs, 2 Fan speed inputs, and one external temperature
inputs. It also integrates the automatic power control logic to control the power ON/OFF for
ATX power supply. In addition, SiS5595 also integrates the thermal detection and frequency
ratio control logic for Pentium II CPU.
3.1
PCI BUS INTERFACE
3.1.1 PCI TO ISA BUS BRIDGE
As a PCI slave device, the PCI-to-ISA Bridge responds to both I/O and memory transfers. It
always target-terminates after the first data phase for any bursting cycle.
The PCI-to-ISA Bridge is assigned as the subtractive decoder in the Bus 0 of the PCI/ISA
system by accepting all accesses not positively decoded by some other agents. In reality, it
only subtractively responds to low 64K I/O or low 16M memory accesses. It also positively
decodes BIOS memory space by asserting DEVSEL# signal on the medium timing. It is
optional to do positive or subtractive decode on I/O addresses for some internal registers.
As a PCI master device, the PCI master bridge on behalf of DMA devices or ISA Master
devices drives the AD bus, C/BE[3:0]# and PAR signals. When MEMR# or MEMW# is
asserted, the PCI-to-ISA bridge will generate FRAME#, and IRDY# to PCI bus if the targeted
memory is not on the ISA side. The valid address and command are driven during the
address phase, and PAR signal is asserted one clock after that phase. It always activates
FRAME# for 2 PCLKs because it does not conduct any bursting cycle.
The ISA address decoder is used to determine the destination of ISA master devices or DMA
devices. This decoder provides the following options as they are defined in registers 48h to
4Bh of PCI to ISA Bridge configuration space.
a. Memory: 0-512K
b. Memory: 512K-640K
c. Memory: 640K-768K (video buffer)
d. Memory: 768K-896K in eight 16K sections (Expansion ROM)
e. Memory: 896K-960K (lower BIOS area)
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