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| 型號： | SIS5595 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Pentium PCI System I/O Chipset |
| 中文描述： | 奔騰的PCI系統(tǒng)I / O芯片 |
| 文件頁數(shù)： | 17/216頁 |
| 文件大小： | 2208K |
| 代理商： | SIS5595 |
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SiS5595 PCI System I/O Chipset
Preliminary V2.0 Nov. 2, 1998 11 Silicon Integrated Systems Corporation
DT_PH_2:
This is the period when the ISA cycle corresponding to the delayed transaction is
undergoing on ISA bus.
DT_PH_3:
From the end of ISA cycle up to the original PCI master successfully retries and
completes the whole delayed transaction.
Note:
the delayed transaction is said to be pending during DT_PH_2 and DT_PH_3.
Traditionally, ISA (DMA) masters request ISA bus by asserting their corresponding DRQs to
DMA controller embedded in the PCI-to-ISA bridge. The PCI-to-ISA bridge will then generate
PHOLD# to system arbiter to request for PCI bus. The PHOLD# will be asserted as long as
DRQ is asserted by the ISA master. In response to PHOLD#, the system arbiter grants PCI
bus to PCI-to-ISA bridge by asserting PHLDA#. The PCI-to-ISA bridge, upon receiving
PHLDA#, will first check if ISA bus is busy or idle. If busy, it will defer the assertion of DACK#
until ISA bus returns to idle. If idle, it will assert the corresponding DACK# immediately to
inform ISA master to start. When ISA master receives DACK#, it can then start its cycles
transferring data to or from PCI (ISA) bus. When ISA master finishes its cycles, it de-asserts
DRQ and then PHOLD# will also be de-asserted immediately. The system arbiter, in
response to the desertion of PHOLD#, will immediately de-assert PHLDA#. This completes
the whole sequence of ISA master cycles.
Delayed Transaction and ISA Master Arbitration Rule
1) When ISA master issues DREQ and there is no pending delayed transaction, this is the
normal case that no arbitration is needed and the PCI-to-ISA bridge behaves exactly as
that stated above.
2) When ISA master issues DREQ and there is currently a delayed transaction pending,
the PCI-to-ISA bridge will disregard the pending delayed transaction and immediately
generate PHOLD# to request for PCI bus.
3) When the system arbiter grants PCI bus to ISA master by asserting PHLDA#, and the
delayed transaction is in DT_PH_2, i.e., the ISA bus is busy, the PCI-to-ISA bridge
should defer the assertion of DACK# until DT_PH_3 is entered. Otherwise, ISA master
will start its cycles as soon as DACK# is asserted and may result in ISA bus conflict.
4) If PHLDA# is asserted when the pending delayed transaction is already in DT_PH_3,
i.e., the ISA bus has returned to idle, the PCI-to-ISA bridge can assert DACK#
immediately and hence ISA master may start its cycles even when the delayed
transaction is not yet completed on PCI bus.
5) During the period that ISA master is active and delayed transaction is pending in
DT_PH_3, the original PCI master that initiated the delayed transaction will temporarily
stop retrying on the PCI bus because PCI bus is now owned by ISA master.
6) After the ISA master finishes its data transfers, the original PCI master should
eventually re-gain PCI bus and retry successfully.
3.1.2 DISTRIBUTED DMA (DDMA)
Distributed DMA allows the individual DMA channels to be separated into different physical
devices on the PCI bus. In distributed DMA, the DMA Master contains the addresses that
were occupied by the traditional ISA DMA Controller (8237). This device will respond to any
system read or write to the traditional ISA DMA address locations so the software will
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