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DSP56853/854/855/857/858 User’s Manual
MOTOROLA
Preliminary
Resets
4
bit in CGM control register is zero), and OSC_LOPWR is asserted high, the OSC module
shuts off its output clock amplifiers for maximum power savings. When the CGM TOD
clock prescaler is used (TOD_SEL bit is one), OSC_LOPWR is ignored because the CGM
depends on clocking from OSC to generate the TOD clock.
When a fast Stop mode recovery is used (the OMR6_SD bit in the core is set) neither
OSC_LOPWR nor PLL_SHUTDOWN will assert during the Stop mode entry. In this
case, the Stop mode entry leaves the clock generation system alone. When there is a return
to the Run mode, the clock (PLL based or direct), will be just as it was when Stop was
entered avoiding any need to wait for PLL lock.
The SIM does not automatically restart and engage the PLL upon recovery from extreme
low power mode. This responsibility is left to the applications software. Refer to the
documentation of the oscillator module for details on its low power mode input.
A final note on timing. Entry into either the Wait or Stop modes occurs at the next system
clock edge after p5STOP or p5WAIT asserts. Their disabling effect on clock generation
will start one clock cycle after that. The timing of entry into low power modes, especially
the Stop mode, is critical and is managed by a state machine in the Power Mode Control
module. This module ensures while in the Stop mode entry, PLL_SHUTDOWN asserts
and the PLL is disabled and in Bypass mode before OSC_LOPWR asserts possibly
shutting off the clock input to the PLL.
4.10 Resets
The SIM supports four sources of reset. The two asynchronous sources are the external
reset pin and the Power-On Reset (POR). The two synchronous sources are the software
reset, generated within the SIM itself, and the COP reset. The reset generation module has
two reset detectors. A chip internal reset is detected when any of the sources assert. A
POR reset is detected only when the POR input asserts. The detectors remain asserted
until the last active reset source deasserts. The chip-internal reset detector output is the
primary reset used within the SIM. The only exception is the software control registers,
reset by the POR reset detector.
The SIM generates four reset outputs. All are active low. These all are activated by one of
the two detectors but remain asserted for 32-system clock cycles after the detector
deasserts. This permits the SIM to generate 32-system clock cycles of continuous clocking
to the part while the reset remains asserted. This is required to clear synchronous resets
within the DSP56800E core and elsewhere in the part. The RST_CORE, RST_PERIPH,
and RST_CGM outputs are activated by the chip-internal reset detector and the RST_TOD
output is activated by the POR reset detector. The RST_CORE output is used to reset the
core. The RST_TOD output is used to reset all controls used to configure time of day