- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄383876 > T7633 (Lineage Power) Dual T1/E1 3.3 V Short-Haul Terminator(雙T1/E1 3.3V短通信距離終端器) PDF資料下載
參數(shù)資料
| 型號(hào)： | T7633 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 3.3 V Short-Haul Terminator(雙T1/E1 3.3V短通信距離終端器) |
| 中文描述： | 雙T1/E1的3.3伏短途終結(jié)者（雙T1/E1的3.3短通信距離終端器） |
| 文件頁(yè)數(shù)： | 122/248頁(yè) |
| 文件大?。?/td> | 1459K |
| 代理商： | T7633 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)當(dāng)前第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)
Advance Data Sheet
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
May 1998
112
Lucent Technologies Inc.
Facility Data Link (FDL)
(continued)
Receive Facility Data Link Interface
(continued)
Receive HDLC Mode
This is the default mode of the FDL. The receive FDL receives serial data from the receive framer, identifies HDLC
frames, reconstructs data bytes, provides bit destuffing as necessary, and loads parallel data in the receive FIFO.
The receive queue manager forms a status of frame (SF) byte for each HDLC frame and stores the SF byte in the
receive FDL FIFO (register FDL_SR4) after the last data byte of the associated frame. HDLC frames consisting of
n bytes will have n + 1 bytes stored in the receive FIFO. The frame check sequence bytes (CRC) of the received
HDLC frame are not stored in the receive FIFO. When receiving ANSI PRM frames, the frame check sequence
bytes are stored in the receive FIFO.
The SF byte has the following format.
Bit 7 of the SF status byte is the CRC status bit. A 1 indicates that an incorrect CRC was detected. A 0 indicates
the CRC is correct. Bit 6 of the SF status byte is the abort status. A 1 indicates the frame associated with this status
byte was aborted (i.e., the abort sequence was detected after an opening flag and before a subsequent closing
flag). An abort can also cause bits 7 and/or 4 to be set to 1. An abort is not reported when a flag is followed by
seven 1s. Bit 5 is the FIFO overrun bit. A 1 indicates that a receive FIFO overrun occurred (the 64-byte FIFO size
was exceeded). Bit 4 is the FIFO bad byte count that indicates whether or not the bit count received was a multiple
of eight (i.e., an integer number of bytes). A 1 indicates that the bit count received after 0-bit deletion was not a
multiple of eight, and a 0 indicates that the bit count was a multiple of eight. When a non-byte-aligned frame is
received, all bits received are present in the receive FIFO. The byte before the SF status byte contains less than
eight valid data bits. The HDLC block provides no indication of how many of the bits in the byte are valid. User
application programming controls processing of non-byte-aligned frames. Bit 3—bit 0 of the SF status byte are not
used and are set to 0. A good frame is implied when the SF status byte is 00 (hex).
Receive FDL FIFO
Whenever an SF byte is present in the receive FIFO, the end of frame registers FDL_SR0 bit 4 (FREOF) and
FDL_SR2 bit 7 (FEOF) bits are set. The receiver queue status (register FDL_SR2 bit 0—bit 6) bits report the
number of bytes up to and including the first SF byte. If no SF byte is present in the receive FIFO, the count directly
reflects the number of data bytes available to be read. Depending on the FDL frame size, it is possible for multiple
frames to be present in the receive FIFO. The receive fill level indicator register FDL_PR6 bit 0—bit 5 (FRIL) can be
programmed to tailor the service time interval to the system. The receive FIFO full register FDL_SR0 bit 3 (FRF)
interrupt is set in the interrupt status register when the receive FIFO reaches the preprogrammed full position. An
FREOF interrupt is also issued when the receiver has identified the end of frame and has written the SF byte for
that frame. An FDL overrun interrupt register FDL_SR0 bit 5 (FROVERUN) is generated when the receiver needs
to write either status or data to the receive FIFO while the receive FIFO is full. An overrun condition will cause the
last byte of the receive FIFO to be overwritten with an SF byte indicating the overrun status. A receive idle register
FDL_SR0 bit 6 (FRIDL) interrupt is issued whenever 15 or more continuous 1s have been detected.
Table 54. Receive Status of Frame Byte
RSF B7
BAD CRC
RSF B6
ABORT
RSF B5
RFIFO
OVERRUN
RSF B4
BAD BYTE
COUNT
RSF B3
0
RSF B2
0
RSF B1
0
RSF B0
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T7688 | 5.0 V E1/CEPT Quad Line Interface(5.0 V E1/CEPT四線(xiàn)接口) |
| T7689 | 5.0 V T1 Quad Line Interface(5.0 V T1四線(xiàn)接口) |
| T7690 | 5.0 V T1/E1 Quad Line Interface(5.0 V T1/E1 四線(xiàn)接口) |
| T7693 | 3.3 V T1/E1 Quad Line Interface( 3.3 V T1/E四線(xiàn)接口) |
| T7698 | Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線(xiàn)接口和八T1/E1監(jiān)控器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T7645036 | 功能描述:手工工具 Campbell Snap Link #2450, 7/16", Steel RoHS:否 制造商:Molex 產(chǎn)品:Extraction Tools 類(lèi)型: 描述/功能:Extraction tool |
| T7645106 | 制造商:COOPER INDUSTRIES 功能描述:CC ACCESYS / #7350 1/8 Quick Link Steel Zinc Plated UPC Tagged |
| T7645126 | 制造商:COOPER INDUSTRIES 功能描述:CC ACCESYS / #7350 1/4 Quick Link Steel Zinc Plated UPC Tagged |
| T7645136V | 制造商:COOPER INDUSTRIES 功能描述:CC ACCESYS / #7350 5/16 Quick Link Steel Zinc Plated UPC Tagged |
| T7645146 | 制造商:COOPER INDUSTRIES 功能描述:CC ACCESYS / #7350 3/8 Quick Link Steel Zinc Plated UPC Tagged |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。