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| 型號： | T7633 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 3.3 V Short-Haul Terminator(雙T1/E1 3.3V短通信距離終端器) |
| 中文描述： | 雙T1/E1的3.3伏短途終結者（雙T1/E1的3.3短通信距離終端器） |
| 文件頁數(shù)： | 123/248頁 |
| 文件大?。?/td> | 1459K |
| 代理商： | T7633 |
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Advance Data Sheet
May 1998
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
113
Lucent Technologies Inc.
Facility Data Link (FDL)
(continued)
Receive Facility Data Link Interface
(continued)
The receive queue status bits, register FDL_SR2 bit 0—bit 6 (FRQS), are updated as bytes are loaded into the
receive FIFO. The SF status byte is included in the byte count. When the first SF status byte is placed in the FIFO,
register FDL_SR0 bit 4 (FREOF) is set to 1, and the status freezes until the FIFO is read. As bytes are read from
the FIFO, the queue status decrements until it reads 1. The byte read when register FDL_SR2 bit 0—bit 6 =
0000001 and the FREOF bit is 1 is the SF status byte describing the error status of the frame just read. Once the
first SF status byte is read from the FIFO, the FIFO status is updated to report the number of bytes to the next SF
status byte, if any, or the number of additional bytes present. When FREOF is 0, no SF status byte is currently
present in the FIFO, and the FRQS bits report the number of bytes present. As bytes are read from the FIFO, the
queue status decrements with each read until it reads 0 when the FIFO is totally empty. The FREOF bit is also 0
when the FIFO is completely empty. Thus, the FRQS and FREOF bit provide a mechanism to recognize the end of
1 frame and the beginning of another. Reading the FDL receiver status register does not affect the FIFO buffers. In
the event of a receiver overrun, an SF status byte is written to the receive FIFO. Multiple SF status bytes can be
present in the FIFO. The FRQS reports only the number of bytes to the first SF status byte.
To allow users to tailor receiver FIFO service intervals to their systems, the receiver interrupt level bits in register
FDL_PR6 bit 0—bit 5 (FRIL) are provided. These bits are coded in binary and determine when the receiver full
interrupt, register FDL_SR0 bit 3 (FRF), is asserted. The interrupt pin transition can be masked by setting register
FDL_PR2 bit 3 (FRFIE) to 0. The value programmed in the FRIL bits equals the total number of bytes necessary to
be present in the FIFO to trigger an FRF interrupt. The FRF interrupt alone is not sufficient to determine the
number of bytes to read, since some of the bytes may be SF status bytes. The FRQS bits and FREOF bit allow the
user to determine the number of bytes to read. The FREOF interrupt can be the only interrupt for the final frame of
a group of frames, since the number of bytes received to the end of the frame cannot be sufficient to trigger an FRF
interrupt.
Programming Note:
Since the receiver writing to the receive FIFO and the host reading from the receive FIFO are
asynchronous events, it is possible for a host read to put the number of bytes in the receive FIFO just below the
programmed FRIL level and a receiver write to put it back above the FRIL level. This causes a new FRF interrupt,
and has the potential to cause software problems. It is recommended that during service of the FRF interrupt, the
FRF interrupt be masked FRFIE = 0, and the interrupt register be read at the end of the service routine, discarding
any FRF interrupt seen, before unmasking the FRF interrupt.
Receiver Overrun
A receiver overrun occurs if the 64-byte limit of the receiver FIFO is exceeded, i.e., data has been received faster
than it has been read out of the receive FIFO. Upon overrun, an SF status byte with the overrun bit (bit 5) set to 1
replaces the last byte in the FIFO. The SF status byte can have other error conditions present. For example, it is
unlikely the CRC is correct. Thus, care should be taken to prioritize the possible frame errors in the software
service routine. The last byte in the FIFO is overwritten with the SF status byte regardless of the type of byte (data
or SF status) being overwritten. The overrun condition is reported in register FDL_SR0 bit 5 and causes the
interrupt pin to be asserted if it is not masked (register FDL_PR2 bit 5 (FROVIE)). Data is ignored until the
condition is cleared and a new frame begins. The overrun condition is cleared by reading register FDL_SR0 bit 5
and reading at least 1 byte from the receive FIFO. Because multiple frames can be present in the FIFO, good
frames as well as the overrun frame can be present. The host can determine the overrun frame by looking at the
SF status byte.
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