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Advance Data Sheet
May 1998
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
71
Lucent Technologies Inc.
Frame Formats
(continued)
CEPT Time Slot 0 CRC-4 Multiframe Structure
(continued)
The CRC-4 word, located in submultiframe N, is the remainder after multiplication by x
4
and then division
(modulo 2) by the generator polynomial x
4
+ x + 1, of the polynomial representation of the submultiframe N – 1.
Representing the contents of the submultiframe check block as a polynomial, the first bit in the block, i.e., frame 0,
bit 1 or frame 8, bit 1, is taken as being the most significant bit and the least significant bit in the check block is
frame 7 or frame 15, bit 256. Similarly, C
1
is defined to be the most significant bit of the remainder and C
4
the least
significant bit of the remainder. The encoding procedure, as described in ITU Rec. G.704 Section 2.3.3.5.2, fol-
lows:
1.
The CRC-4 bits in the SMF are replaced by binary 0s.
2.
The SMF is then acted upon the multiplication/division process referred to above.
3.
The remainder resulting from the multiplication/division process is stored, ready for insertion into the respec-
tive CRC-4 locations of the next SMF.
The decoding procedure, as described in ITU Rec. G.704 Section 2.3.3.5.3, follows:
1.
A received SMF is acted upon by the multiplication/division process referred to above, after having its CRC-4
bits extracted and replaced by 0s.
2.
The remainder resulting from this division process is then stored and subsequently compared on a bit-by-bit
basis with the CRC bits received in the next SMF.
3.
If the remainder calculated in the decoder exactly corresponds to the CRC-4 bits received in the next SMF, it is
assumed that the checked SMF is error-free.
CEPT Loss of CRC-4 Multiframe Alignment (LTS0MFA)
Loss of basic frame alignment forces the receive framer into a loss of CRC-4 multiframe alignment state. This state
is reported by way of the status registers FRM_SR1 bit 2. Once basic frame alignment is achieved, a new search
for CRC-4 multiframe alignment is initiated. During a loss of CRC-4 multiframe alignment state:
1. The CRC-4 error counter is halted.
2. The CRC-4 error monitoring circuit for errored seconds and severely errored seconds is halted.
3. The received E-bit counter is halted.
4. The received E-bit monitoring circuit for errored seconds and severely errored seconds at the remote end
interface is halted.
5. Receive continuous E-bit monitoring is halted.
6. All receive Sa6 code monitoring and counting functions are halted.
7. The updating of the receive Sa stack is halted and the receive Sa stack interrupt is deactivated.
8. Optionally, A = 1 may be automatically transmitted to the line if register FRM_PR27 bit 2 is set to 1.
9. Optionally, E = 0 may be automatically transmitted to the line if register FRM_PR28 bit 4 is set to 1.
10. Optionally, if LTS0MFA monitoring in the performance counters is enabled, by setting registers FRM_PR14
through FRM_PR17 bit 1 to 1, then these counts are incremented once per second for the duration of the
LTS0MFA state.