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參數(shù)資料
| 型號(hào)： | T7633 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 3.3 V Short-Haul Terminator(雙T1/E1 3.3V短通信距離終端器) |
| 中文描述： | 雙T1/E1的3.3伏短途終結(jié)者（雙T1/E1的3.3短通信距離終端器） |
| 文件頁(yè)數(shù)： | 152/248頁(yè) |
| 文件大?。?/td> | 1459K |
| 代理商： | T7633 |
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Advance Data Sheet
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
May 1998
142
Lucent Technologies Inc.
Microprocessor Interface
(continued)
Microprocessor Clock (MPCLK) Specifications
The microprocessor interface is designed to operate at clock speeds up to 33 MHz without requiring any wait-
states. Wait-states may be needed if higher microprocessor clock speeds are required. The microprocessor clock
(MPCLK, pin 101) specification is shown in Table 67. This clock must be supplied only if the RDY (MODE 3 and
MODE 4) is required to be synchronous to MPCLK.
Microprocessor Interface Register Address Map
The register address space is divided into eight (8) contiguous banks of 512 addressable units each. Each
addressable unit is an 8-bit register. These register banks are labeled as REGBANK[7:0]. The register address
map table gives the address range of these register banks and their associated circuit blocks. REGBANK0 con-
tains the global registers which are common to all the circuit blocks on T7633. REGBANK1 is reserved and must
not be written. REGBANK[2, 5] are attached to the LIU circuit blocks. REGBANK[3, 6] are attached to the framer
circuit blocks. REGBANK[4, 7] are attached to the FDL circuit blocks. The descriptions of the individual register
banks can be found in the appropriate sections of this document. In these descriptions, all addresses are given in
hexadecimal.
Addresses out of the range specified by Table 68 must not be addressed. If they are written,
they must be written to 0. An inadvertant write to an out-of-range address may be corrected by a device
reset.
1.Core registers are common to all circuit blocks on T7633.
I/O Timing
The I/O timing specifications for the microprocessor interface are given in Table 69. The microprocessor interface
pins are compatible with CMOS/TTL I/O levels. All outputs, except the address/data bus AD[7:0], are rated for a
capacitive load of 50 pF. The AD[7:0] outputs are rated for a 100 pF load.
Table 67. Microprocessor Input Clock Specifications
Name
Symbol
Period
and
Tolerance
T
rise
Typ
T
fall
Typ
Duty Cycle
Unit
Min High
Min Low
MPCLK
t1
30 to 323
2
2
12
12
ns
Table 68. T7633 Register Address Map
Register Bank Label
Start Address
(in Hex)
000
—
400
600,
6E0
800
A00
C00,
CE0
E00
End Address
(in Hex)
007
—
406
6A6,
6FF
80E
A06
CA6,
CFF
E0E
Circuit Block Name
REGBANK0
REGBANK1
REGBANK2
REGBANK3
T7633 Global Registers
1
Reserved
Line Interface Unit 1 (LIU1)
Framer1
REGBANK4
REGBANK5
REGBANK6
Facility Data Link 1 (FDL1)
Line Interface Unit 2 (LIU2)
Framer2
REGBANK7
Facility Data Link 2 (FDL2)
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