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Advance Data Sheet
May 1998
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
235
Lucent Technologies Inc.
Index
(continued)
M
Maintenance
LoopBack and Transmission Modes 99, 100, 101
match bit 119
Microprocessor Clock (MPCLK) Specifications 142
microprocessor interface 140
microprocessor modes 140
MPMODE 140
MPMUX 140
N
negative slip 93
Network Termination and Network Termination Remote
End Interface Status Register 172
no CRC-4 79
NOT FAS 80
NOT FAS frames 67
NOT FAS Sa Stack Source and Destination 82, 83, 84
NOT FAS Sa4 bit Sources 80
NT1 Bursty Errored Seconds Counter 176
NT1 Errored Event Enable Register 187
NT1 Errored Seconds Counter 176
NT1 Remote End Errored Event Enable Register 187
NT1 Severely Errored Seconds Counter 176
NT1 Unavailable Seconds Counter 176
NT1-RE Bursty Errored Seconds Counter 177
NT1-RE Errored Seconds Counter 176
NT1-RE Severely Errored Seconds Counter 177
NT1-RE Unavailable Seconds Counter 177
O
Operating Conditions 228
Ordering 231
Ordering Information 231
Outline Diagram 230
Output Pulse Generation 34
P
Parameters 126, 127, 128
Payload loopback 99
performance report message 108, 115
Performance Report Messages 110
performance report messages 114
phase-lock 122
PLLB 100
positive slip 93
Power Supply 47, 229
Powerdown 45
Primary Block Interrupt Enable Register 155
Primary Block Interrupt Status Register 155
Principle of the Boundary Scan 135
PRM 110
pseudorandom test pattern 102
Pulse Template 37, 38, 39
Q
quasi-random test signal 102
R
Rate adaptation 125
RCE 133
Rec. G.704 66
Receive ANSI FDL Status Register 218
Receive ANSI T1.403 Bit-Oriented Messages 109
Receive CRC-4 Multiframe Search Algorithm Using the
100 ms Internal Timer 73
Receive Facility Data Link Interface 108
Receive FDL FIFO 112
Receive Frame Edge 126
receive framer 50
Receive Framer Reframe 107
Receive HDLC Mode 112
Receive Highway Select 127
Receive Least Significant Bit First 128
receive line elastic store buffer 124
Receive Line Interface Configuration Modes 27
Receive NOT-FAS TS0 Register 177
receive queue status 113
receive Sa stack 71
Receive Signaling Inhibit 107
Receive Signaling Registers
CEPT Format 179
Receive Time-Slot Enable 127
Receive Time-Slot Enable Registers 206
received E-bit counter 71
received end of frame 119
Received Sa Register 177
Received Signaling Registers 179
DS1 Format 179
Receiver Alarms 28, 29
Receiver Bit Offset 127
Receiver Byte Offset 127
Receiver Clock Edge 126
Receiver FDL FIFO Register 218
receiver full 113, 119
receiver idle 119
receiver overrun 113, 119
Red alarm 91
Register Maps 219
remote alarm indication 67
Remote End Alarm Register 167
Remote Frame Alarm 106
remote frame alarm 62, 92
remote loopback 120, 121
Remote Loopback (RLOOP) 44
Reset 149
Return Loss 30, 31
RFE 132, 133
Robbed-Bit Signaling 85