參數資料
型號: TLV320AIC3120IRHBT
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻/視頻放大
英文描述: AUDIO AMPLIFIER, PQCC32
封裝: 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數: 120/150頁
文件大?。?/td> 1507K
代理商: TLV320AIC3120IRHBT
BCLK
WCLK
DIN/DOUT
n-1 n-2
1
0
n-1 n-2
1
0
LSB
MSB
LeftChannel
RightChannel
n-3
2
n-3
LSB
MSB
1/fs
LD(n)
LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
-
2
-
3
2
1
0
3
-
1
-
2
-
3
2
1
0
3
-
1
-
2
N N N
-
3
RD(n)
LEFT CHANNEL
RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata
RD(n)=n'thsampleofrightchanneldata
LD(n)
LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
-
2
-
3
2
1
0
3
-
1
-
2
-
3
2
1
0
3
-
1
-
2
N N N
-
3
RD(n)
LEFT CHANNEL
RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata
RD(n)=n'thsampleofrightchanneldata
www.ti.com
SLAS653 – FEBRUARY 2010
Figure 5-36. Timing Diagram for Right-Justified Mode
For right-justified mode, the number of bit clocks per frame should be greater than or equal to twice the
programmed word length of the data.
5.8.1.2
Left-Justified Mode
The audio interface of the TLV320AIC3120 can be put into left-justified mode by programming page 0 /
register 27, bits D7–D6 = 11. In left-justified mode, the MSB of the right channel is valid on the rising edge
of the bit clock following the falling edge of the word clock. Similarly, the MSB of the left channel is valid
on the rising edge of the bit clock following the rising edge of the word clock.
Figure 5-37. Timing Diagram for Left-Justified Mode
Figure 5-38. Timing Diagram for Left-Justified Mode With Offset = 1
Copyright 2010, Texas Instruments Incorporated
APPLICATION INFORMATION
71
Product Folder Link(s): TLV320AIC3120
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