參數(shù)資料
型號： TLV320AIC3120IRHBT
廠商： TEXAS INSTRUMENTS INC
元件分類： 音頻／視頻放大
英文描述： AUDIO AMPLIFIER, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù)： 68/150頁
文件大小： 1507K
代理商： TLV320AIC3120IRHBT
SLAS653 – FEBRUARY 2010
www.ti.com
Table 5-9. MICBIAS Settings
D1
D0
FUNCTIONALITY
0
MICBIAS output is powered down.
0
1
MICBIAS output is powered to 2 V.
1
0
MICBIAS output is powered to 2.5 V.
1
MICBIAS output is powered to AVDD.
During normal operation, MICBIAS can be set to 2.5 V for better performance. However, depending on the
model of microphone that is selected, optimal performance might be obtained at another setting, so the
performance at a given setting should be verified.
The lowest current consumption occurs when MICBIAS is powered down. The next-lowest current
consumption occurs when MICBIAS is set at AVDD. The highest current consumption occurs when
MICBIAS is set at 2 V.
Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering,
requirements for analog anti-aliasing filtering are very relaxed. The TLV320AIC3120 integrates a
second-order analog anti-aliasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the
digital decimal filter, provides sufficient anti-aliasing filtering without requiring any external components.
The MIC PGA supports analog gain control from from 0 dB to 59.5 dB in steps of 0.5 dB. These gain
levels can be controlled by writing to page 1 / register 47, bits D6–D0. The PGA gain changes are
implemented with internal soft-stepping. This soft-stepping ensures that volume-control changes occur
smoothly with no audible artifacts. On reset, the MIC PGA gain defaults to a mute condition, with soft
stepping enabled. The ADC soft-stepping control can be enabled or disabled by writing to page 0 /
register 81, bits D1–D0. ADC soft-stepping timing is provided by the internal oscillator and internal divider
logic block.
The input feed-forward resistance for the MIC1LP input of the microphone PGA stage has three settings of
10 k
, 20 k, and 40 k, which are controlled by writing to page 1 / register 48, bits D7 and D6. The input
feed-forward resistance value selected affects the gain of the microphone PGA. The ADC PGA gain for
the MIC1LP input depends on the setting of page 1 / register 48 and page 1 / register 49, bits D7–D6. If
D7–D6 are set to 01, then the ADC PGA has 6 dB more gain with respect to the value programmed using
page 1 / register 47. If D7–D6 are set to 10, then the ADC PGA has the same gain as programmed using
page 1 / register 47. If D7–D6 are set to 11, then the ADC PGA has 6 dB less gain with respect to the
value programmed using page 1 / register 47. The same gain scaling is also valid for the MIC1RP and
MIC1LM inputs, based on the feed-forward resistance selected using page 1 / register 48, bits D5–D2.
The MIC PGA gain can be controlled either by an AGC loop or as a fixed gain. See Figure 1-1 for the
various analog input routings to the MIC PGA that are supported in the single-ended and differential
configurations. The AGC can be enabled by writing to page 0 / register 86, bit D7. If the AGC is not
enabled, then setting a fixed gain is done by writing to page 1 / register 47, bits D6–D0. Because the
TLV320AIC3120 supports soft-stepping gain changes, a read-only flag on page 0 / register 36, bit D7 is
set whenever the gain applied by PGA equals the desired value set by the gain register. The MIC PGA
can be enabled by writing to page 1 / register 47, bit D7. ADC muting can be done by writing to page 0 /
register 82, bit D7 and page 1 / register 47, bit D7. Disabling the MIC PGA sets the gain to 0 dB. Muting
the ADC causes the digital output to mute so that the output value remains fixed. When soft-stepping is
enabled, the CODEC_CLKIN signal must stay active until after the ADC power-down register is written, in
order to ensure that soft-stepping to mute has had time to complete. When the ADC POWER UP flag is
no longer set, the CODEC_CLKIN signal can be shut down.
24
APPLICATION INFORMATION
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC3120
相關(guān)PDF資料
PDF描述
TLV320AIC31IRHBRG4 SPECIALTY CONSUMER CIRCUIT, PQCC32
TLV320AIC31IRHBR SPECIALTY CONSUMER CIRCUIT, PQCC32
TLV320AIC31IRHBTG4 SPECIALTY CONSUMER CIRCUIT, PQCC32
TLV320AIC31IRHBT SPECIALTY CONSUMER CIRCUIT, PQCC32
TLV320AIC3253IRGER SPECIALTY CONSUMER CIRCUIT, PQCC24
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLV320AIC31EVM 功能描述:音頻 IC 開發(fā)工具 TLV320AIC31 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V
TLV320AIC31EVM-PDK 功能描述:音頻 IC 開發(fā)工具 TLV320AIC31-PDK Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V
TLV320AIC31IRHBR 功能描述:接口—CODEC Lo-Pwr Ster Codec for Port Aud/Teleph RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLV320AIC31IRHBRG4 功能描述:接口—CODEC Lo-Pwr Ster Codec for Port Aud/Teleph RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLV320AIC31IRHBT 功能描述:接口—CODEC Lo-Pwr Ster Codec for Port Aud/Teleph RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*