參數(shù)資料
型號： TLV320AIC3120IRHBT
廠商： TEXAS INSTRUMENTS INC
元件分類： 音頻／視頻放大
英文描述： AUDIO AMPLIFIER, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù)： 135/150頁
文件大?。?/td> 1507K
代理商： TLV320AIC3120IRHBT
www.ti.com
SLAS653 – FEBRUARY 2010
Page 0 / Register 26 (0x1A): CLKOUT M Divider Value
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
0: CLKOUT M divider is powered down.
1: CLKOUT M divider is powered up.
D6–D0
R/W
000 0001
000 0000: CLKOUT divider M = 128
000 0001: CLKOUT divider M = 1
000 0010: CLKOUT divider M = 2
...
111 1110: CLKOUT divider M = 126
111 1111: CLKOUT divider M = 127
Page 0 / Register 27 (0x1B): Codec Interface Control
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D6
R/W
00
00: Codec interface = I2S
01: Codec Interface = DSP
10: Codec interface = RJF
11: Codec interface = LJF
D5–D4
R/W
00
00: Codec interface word length = 16 bits
01: Codec interface word length = 20 bits
10: Codec interface word length = 24 bits
11: Codec interface word length = 32 bits
D3
R/W
0
0: BCLK is input.
1: BCLK is output.
D2
R/W
0
0: WCLK is input.
1: WCLK is output.
D1
R/W
0
Reserved
D0
R/W
0
Driving DOUT to High-Impedance for the Extra BCLK Cycle When Data Is Not Being Transferred
0: Disabled
1: Enabled
Page 0 / Register 28 (0x1C): Data-Slot Offset Programmability
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
0000 0000
Offset (Measured With Respect to WCLK Rising Edge in DSP Mode)
0000 0000: Offset = 0 BCLKs
0000 0001: Offset = 1 BCLK
0000 0010: Offset = 2 BCLKs
...
1111 1110: Offset = 254 BCLKs
1111 1111: Offset = 255 BCLKs
Page 0 / Register 29 (0x1D): Codec Interface Control 2
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D6
R/W
00
Reserved
D5
R/W
0
0: DIN-to-DOUT loopback is disabled.
1: DIN-to-DOUT loopback is enabled.
D4
R/W
0
0: ADC-to-DAC loopback is disabled.
1: ADC-to-DAC loopback is enabled.
D3
R/W
0
0: BCLK is not inverted (valid for both primary and secondary BCLK).
1: BCLK is inverted (valid for both primary and secondary BCLK).
D2
R/W
0
BCLK and WCLK Active Even With Codec Powered Down (Valid for Both Primary and Secondary
BCLK)
0: Disabled
1: Enabled
D1–D0
R/W
00
00: BDIV_CLKIN = DAC_CLK (DAC DSP clock - generated on-chip)
01: BDIV_CLKIN = DAC_MOD_CLK (generated on-chip)
10: BDIV_CLKIN = ADC_CLK (ADC DSP clock - generated on-chip)
11: BDIV_CLKIN = ADC_MOD_CLK (generated on-chip)
Copyright 2010, Texas Instruments Incorporated
REGISTER MAP
85
Product Folder Link(s): TLV320AIC3120
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TLV320AIC31IRHBRG4 功能描述:接口—CODEC Lo-Pwr Ster Codec for Port Aud/Teleph RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
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