參數(shù)資料
型號(hào)： TLV320AIC3120IRHBT
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 音頻／視頻放大
英文描述： AUDIO AMPLIFIER, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁(yè)數(shù)： 130/150頁(yè)
文件大?。?/td> 1507K
代理商： TLV320AIC3120IRHBT
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SLAS653 – FEBRUARY 2010
www.ti.com
6
REGISTER MAP
6.1
TLV320AIC3120 Register Map
All features on this device are addressed using the I2C bus. All of the writable registers can be read back.
However, some registers contain status information or data, and are available for reading only.
The TLV320AIC3120 contains several pages of 8-bit registers, and each page can contain up to 128
registers. The register pages are divided up based on functional blocks for this device. Page 0 is the
default home page after RESET. Page control is done by writing a new page value into register 0 of the
current page.
The control registers for the TLV320AIC3120 are described in detail as follows. All registers are 8 bits in
width, with D7 referring to the most-significant bit of each register, and D0 referring to the least-significant
bit.
Pages 0, 1, 3–5, 8–15, 32–43, and 64–95 are available for use; however, all other pages and registers are
reserved. Do not read from or write to reserved pages and registers. Also, do not write other than the
reset values for the reserved bits and read-only bits of non-reserved registers; otherwise, device
functionality failure can occur.
Note that the page and register numbers are shown in decimal format. For use in microcode, these
decimal values may need to be converted to hexadecimal format. For convienience, the register
numbers are shown in both formats, whereas the page numbers are shown only in decimal format.
Table 6-1. Summary of Register Map
Page Number
Description
Page 0 is the default page on power up. Configuration for serial interface, digital I/O, clocking, ADC, DAC, miniDSP
0
settings, etc.
1
Configuration for analog PGAs, ADC, DAC, output drivers, volume controls, etc.
Register 16 controls the MCLK divider that controls the interrupt pulse duration, debounce timing, and detection block
3
clock.
4–5
ADC AGC and filter coefficients
8–11
DAC buffer A filter and DRC coefficients
12–15
DAC buffer B filter and DRC coefficients
32–43
ADC miniDSP instruction RAM locations
64–95
DAC miniDSP instruction RAM locations
6.2
Control Registers, Page 0 (Default Page): Clock Multipliers, Dividers, Serial
Interfaces, Flags, Interrupts, and GPIOs
Page 0 / Register 0 (0x00): Page Control Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
0000 0000
0000 0000: Page 0 selected
0000 0001: Page 1 selected
...
1111 1110: Page 254 selected
1111 1111: Page 255 selected
Page 0 / Register 1 (0x01): Software Reset
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D1
R/W
0000 000
Reserved. Write only zeros to these bits.
D0
R/W
0
0: Don't care
1: Self-clearing software reset for control register
80
REGISTER MAP
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC3120
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