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| 型號： | TLV320AIC3120IRHBT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | AUDIO AMPLIFIER, PQCC32 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件頁數(shù)： | 71/150頁 |
| 文件大?。?/td> | 1507K |
| 代理商： | TLV320AIC3120IRHBT |
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SLAS653 – FEBRUARY 2010
One example of AGC code follows, but actual use of code should be verified based on application usage.
Note that the AGC code should be set up before powering up the ADC.
####################### AGC Enable Example I2C Script #####################
## Switch to Page 0
w 30 00 00
# Set AGC enable and Target Level = -10 dB
# Target level can be set lower if clipping occurs during speech
# Target level is adjusted considering Max Gain also
w 30 56 A0
# AGC hysteresis=DISABLE, noise threshold = -90dB
# Noise threshold should be set at higher level if noisy background is present in application
w 30 57 FE
# AGC maximum gain= 40 dB
# Higher Max gain is a trade off between gaining up a low sensitivity MIC, and the background
# acoustic noise
# Microphone bias voltage (MICBIAS) level can be used to change the Microphone Sensitivity
w 30 58 50
# Attack time=864/Fs
w 30 59 68
# Decay time=22016/Fs
w 30 5A A8
# Noise debounce 0 ms
# Noise debounce time can be increased if needed
w 30 5B 00
# Signal debounce 0 ms
# Signal debounce time can be increased if needed
w 30 5C 00
######################## END of AGC SET UP #################################
5.5.3
Delta-Sigma ADC
The analog-to-digital converter has a delta-sigma modulator with an oversampling ratio (AOSR) up to 128.
The ADC can support a maximum output rate of 192 kHz.
ADC power up is controlled by writing to page 0 / register 81, bit D7. An ADC power-up condition can be
verified by reading page 0 / register 36, bit D6.
5.5.4
ADC Decimation Filtering and Signal Processing
The TLV320AIC3120 ADC channel includes built-in digital decimation filters to process the oversampled
data from the delta-sigma modulator to generate digital data at the Nyquist sampling rate with high
dynamic range. The decimation filter can be chosen from three different types, depending on the required
frequency response, group delay, and sampling rate.
5.5.4.1
ADC Processing Blocks
The TLV320AIC3120 offers a range of processing blocks which implement various signal processing
capabilities along with decimation filtering. These processing blocks give users the choice of how much
and what type of signal processing they may use and which decimation filter is applied.
The choices among these processing blocks allow the system designer to balance power conservation
and signal-processing flexibility. Less signal-processing capability reduces the power consumed by the
device. Table 5-11 gives an overview of the available processing blocks of the ADC channel and their
properties. The Resource Class (RC) column gives an approximate indication of power consumption.
The signal processing blocks available are:
First-order IIR
Scalable number of biquad filters
Variable-tap FIR filter
AGC
The processing blocks are tuned for common cases and can achieve high anti-alias filtering or low group
delay in combination with various signal-processing effects such as audio effects and frequency shaping.
The available first-order IIR, biquad, and FIR filters have fully user-programmable coefficients.
Copyright 2010, Texas Instruments Incorporated
APPLICATION INFORMATION
27
Product Folder Link(s): TLV320AIC3120
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