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參數(shù)資料
| 型號： | TMS28F002AXY |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES |
| 中文描述： | 262144按8-BIT/131072由16位自動(dòng)選擇啟動(dòng)塊閃存 |
| 文件頁數(shù)： | 13/79頁 |
| 文件大?。?/td> | 1064K |
| 代理商： | TMS28F002AXY |
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TMS28F002Axy, TMS28F200Axy
262144 BY 8-BIT/131072 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997
13
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
byte-wide or word-wide mode selection
(continued)
Table 8. Operation Modes for ’28F002Axy (see Note 1)
MODE
WP
E
G
RP
W
A9
A0
VPP
X
DQ0–DQ7
Read
X
VIL
VIL
VIH
VIH
X
X
Data out
X
VIL
VIL
VIH
VIH
VID
VIL
X
Manufacturer-equivalent code
89h
Algorithm-selection mode
X
VIL
VIL
VIH
VIH
VID
VIH
X
Device-equivalent code 7Ch
(top boot block)
Device-equivalent code 7Dh
(bottom boot block)
Output disable
X
VIL
VIH
X
VIH
X
VIH
VIH
VIL
VIH or
VHH
VIH
X
X
X
X
Hi-Z
Standby
X
X
X
X
Hi-Z
Reset/deep power-down
X
X
X
X
X
X
Hi-Z
Write (see Note 3)
VIL or
VIH
VIL
VIH
VIL
X
X
VPPL or
VPPH
Data in
NOTES:
1. X = don’t care
3. When writing commands to the ’28F002Axy, VPP must be in the appropriate VPP voltage range (as shown in the recommended
operating conditions table for the product) for block-erase or program commands to be executed. Also, depending on the
combination of RP and WP, the boot block can be secured and, therefore, is not programmable (see Table 2 for the combinations).
command-state-machine operations
The CSM decodes instructions for read, read algorithm-selection code, read status register, clear status
register, program, erase, erase-suspend, and erase-resume. The 8-bit command code is input to the device on
DQ0–DQ7 (see Table 3 for CSM codes). During a program or erase cycle, the CSM informs the WSM that a
program or erase cycle has been requested. During a program cycle, the WSM controls the program sequences
and the CSM responds only to status reads.
During an erase cycle, the CSM responds to status-read and erase-suspend commands. When the WSM has
completed its task, the WSM status bit (SB7) is set to a logic-high level and the CSM responds to the full
command set. The CSM stays in the current command state until the microprocessor issues another command.
The WSM successfully initiates an erase or program operation only when V
PP
is within its correct voltage range.
For data protection, it is recommended that RP be held at a logic-low level during a CPU reset.
clear status register
The internal circuitry can set only the V
PP
status (SB3), the program status bit (SB4), and the erase status bit
(SB5) of the status register. The clear-status-register command (50h) allows the external microprocessor to
clear these status bits and synchronize to internal operations. When the status bits are cleared, the device
returns to the read-array mode.
read operations
There are three read operations available: read array, read algorithm-selection code, and read status register.
read array
The array level is read by entering the command code FFh on DQ0–DQ7. Control pins E and G must be at a
logic-low level (V
IL
) and W and RP must be at a logic-high level (V
IH
) to read data from the array. Data is
available on DQ0–DQ15 (word-wide mode) or DQ0–DQ7 (byte-wide mode). Any valid address within any
of the blocks selects that block and allows data to be read from the block.
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