參數(shù)資料
型號： TMS28F002AXY
廠商： Texas Instruments, Inc.
英文描述： 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
中文描述： 262144按8-BIT/131072由16位自動選擇啟動塊閃存
文件頁數(shù)： 8/79頁
文件大?。?/td> 1064K
代理商： TMS28F002AXY
TMS28F002Axy, TMS28F200Axy
262144 BY 8-BIT/131072 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997
8
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
parameter block
Two parameter blocks of 8K bytes each can be used like a scratch pad to store frequently updated data.
Alternatively, the parameter blocks can be used for additional boot-block or main-block data. If a parameter
block is used to store additional boot-block data, caution must be exercised because the parameter block does
not have the boot-block data-protection safety feature.
main block
Primary memory on the TMS28F200Axy is located in two main blocks. One of the blocks has storage capacity
for 128K bytes and the other block has storage capacity for 96K bytes.
data protection
Data is secured or unsecured by using different combinations of the reset/deep power-down pin (RP), the
write-protect pin (WP), and V
PP
supply levels. Table 2 shows a listing of these combinations.
There are two configurations to secure the entire memory against the inadvertent alteration of data. The V
PP
supply pin can be held below the V
PP
lock-out voltage level (V
PPLK
) or the reset/deep power-down pin (RP) can
be pulled to a logic-low level. If RP is held low, the device resets—which means that it powers down, and
therefore, cannot be read. Typically this pin is tied to the system reset for additional protection during system
power up.
The boot-block sector has an additional security feature through the WP pin on the ’ASy, ’AEy, and ’AFy devices.
When the RP pin is at a logic-high level, the WP pin controls whether the boot-block sector is protected. When
WP is held at the logic-low level, the boot block is protected. When WP is held at the logic-high level, the boot
block is unprotected, along with the rest of the other sectors. Alternatively, the entire memory for all voltage
configurations can be unprotected by pulling the RP pin to V
HH
(12 V).
Table 2. Data-Protection Combinations
DATA-PROTECTION
PROVIDED
’ASy, ’AEy, or ’AFy
RP
’AMy or ’AZy
RP
VPP
VIL
X
WP
VPP
VIL
X
WP
All blocks locked
X
X
X
X
All blocks locked (reset)
VIL
VHH
VIH
VIH
X
VIL
X
All blocks unlocked
> VPPLK
X
VIH
VIL
VHH
VHH
X
Only boot block locked
For TMS28F200AZy and TMS28F200AMy (12-V VPP) products, the WP pin is disabled and can be left floating. To unlock blocks, RP must
be at VHH.
command-state machine (CSM)
> VPPLK
VHH
VIH
X
Commands are issued to the CSM using standard microprocessor write timings. The CSM acts as an interface
between the external microprocessor and the internal write state machine (WSM). The available commands
are listed in Table 3 and the descriptions of these commands are listed in Table 4. When a program or erase
command is issued to the CSM, the WSM controls the internal sequences and the CSM only responds to status
reads. After the WSM completes its task, the write status bit (WSM) (SB7) is set to a logic-high level, allowing
the CSM to respond to the full command set again.
operation
Device operations are selected by entering standard JEDEC 8-bit command codes with conventional
microprocessor timing into an on-chip CSM through I/O pins DQ0–DQ7. When the device is powered up,
internal reset circuitry initializes the chip to a read-array mode of operation. Changing the mode of operation
requires that a command code be entered into the CSM. Table 3 lists the CSM codes for all modes of operation.
相關(guān)PDF資料
PDF描述
TMS28F004AEB60BDBJL 524288 BY 8-BIT/262144 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
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