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| 型號： | TMS28F002AXY |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES |
| 中文描述： | 262144按8-BIT/131072由16位自動選擇啟動塊閃存 |
| 文件頁數(shù)： | 58/79頁 |
| 文件大?。?/td> | 1064K |
| 代理商： | TMS28F002AXY |
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TMS28F002Axy, TMS28F200Axy
262144 BY 8-BIT/131072 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997
58
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing requirements for TMS28F002AFy and TMS28F200AFy (commercial and extended
temperature ranges)
write/erase operations — E-controlled writes
ALT.
’28F002AFy60
’28F200AFy60
’28F002AFy70
’28F200AFy70
’28F002AFy80
’28F200AFy80
SYMBOL
5-V VCC
RANGE
5-V VCC
RANGE
5-V VCC
RANGE
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
tc(E)
tc(E)OP
tc(E)ERB
tc(E)ERP
tc(E)ERM
td(RPR)
th(A)
th(D)
th(W)
th(VPP)
Cycle time, write
tAVAV
tEHQV1
tEHQV2
tEHQV3
tEHQV4
tPHBR
tEHAX
tEHDX
tEHWH
tQVVL
60
70
80
ns
μ
s
s
Cycle time, duration of programming operation
6
6
6
Cycle time, erase operation (boot block)
0.3
0.3
0.3
Cycle time, erase operation (parameter block)
0.3
0.3
0.3
s
Cycle time, erase operation (main block)
0.6
0.6
0.6
s
Delay time, boot-block relock
100
100
100
ns
Hold time, A0–A16 (see Note 15)
0
0
0
ns
Hold time, DQ valid
0
0
0
ns
Hold time, W
0
0
0
ns
Hold time, VPP from valid status-register bit
Hold time, RP at VHH from valid status-register
bit
0
0
0
ns
th(RP)
tQVPH
0
0
0
ns
th(WP)
tsu(WP)
tsu(A)
tsu(D)
tsu(W)
tsu(RP)
tsu(VPP)2
tw(E)
tw(EH)
trec(RPHE)
NOTE 15: A–1–A16 for byte-wide
Hold time, WP from valid status-register bit
tWHPL
tELPH
tAVEH
tDVEH
tWLEL
tPHHEH
tVPEH
tELEH
tEHEL
tPHEL
0
0
0
ns
Setup time, WP before write operation
50
50
50
ns
Setup time, A0–A16 (see Note 15)
50
50
50
ns
Setup time, DQ valid
50
50
50
ns
Setup time, W before write operation
0
0
0
ns
Setup time, RP at VHH to E going high
Setup time, VPP to E going high
Pulse duration, E low
100
100
100
ns
100
100
100
ns
50
50
50
ns
Pulse duration, E high
10
20
30
ns
Recovery time, RP high to E going low
450
450
450
ns
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