參數(shù)資料
型號： TMS320C2812ZHHS
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號處理
英文描述： 16-BIT, 150 MHz, OTHER DSP, PBGA179
封裝： LEAD FREE, BGA-179
文件頁數(shù)： 33/156頁
文件大?。?/td> 1826K
代理商： TMS320C2812ZHHS
Electrical Specifications
128
April 2001 Revised October 2005
SPRS174M
6.25
External Interface Write Timing
Table 632. External Memory Interface Write Switching Characteristics
PARAMETER
MIN
MAX
UNIT
td(XCOH-XZCSL)
Delay time, XCLKOUT high to zone chip-select active low
1
ns
td(XCOHL-XZCSH)
Delay time, XCLKOUT high or low to zone chip-select inactive high
2
3
ns
td(XCOH-XA)
Delay time, XCLKOUT high to address valid
2
ns
td(XCOHL-XWEL)
Delay time, XCLKOUT high/low to XWE low
2
ns
td(XCOHL-XWEH)
Delay time, XCLKOUT high/low to XWE high
2
ns
td(XCOH-XRNWL)
Delay time, XCLKOUT high to XR/W low
1
ns
td(XCOHL-XRNWH)
Delay time, XCLKOUT high/low to XR/W high
2
1
ns
ten(XD)XWEL
Enable time, data bus driven from XWE low
0
ns
td(XWEL-XD)
Delay time, data valid after XWE active low
4
ns
th(XA)XZCSH
Hold time, address valid after zone chip-select inactive high
ns
th(XD)XWE
Hold time, write data valid after XWE inactive high
TW2
ns
tdis(XD)XRNW
Maximum time for DSP to release the data bus after XR/W inactive high
4
ns
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
TW = Trail period, write access. See Table 628.
Lead
Active
Trail
td(XCOH-XZCSL)
td(XCOH-XA)
td(XCOHL-XWEL)
td(XCOHL-XWEH)
td(XCOHL-XZCSH)
ten(XD)XWEL
th(XD)XWEH
tdis(XD)XRNW
XCLKOUT=XTIMCLK
XCLKOUT=1/2 XTIMCLK
XZCS0AND1, XZCS2,
XZCS6AND7
XA[0:18]
XRD
XWE
XR/W
XD[0:15]
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment
cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. For USEREADY = 0, the external XREADY input signal is ignored.
D. XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles.
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
DOUT
XREADY
td(XWEL-XD)
Figure 631. Example Write Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
N/A
0
≥1
≥0
N/A
N/A = “Don’t care” for this example
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相關代理商/技術參數(shù)
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TMS320C28341 制造商:TI 制造商全稱:Texas Instruments 功能描述:Delfino Microcontrollers
TMS320C28341ZEPQ 制造商:Texas Instruments 功能描述:DELFINO MICROCONTROLLER - Trays
TMS320C28341ZFEQ 功能描述:32位微控制器 - MCU Delfino MCU RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT
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