參數(shù)資料
型號(hào)： TS68230CP10
廠商： 意法半導(dǎo)體
英文描述： HMOS PARALLEL INTERFACE/TIMER
中文描述： HMO的并行接口/定時(shí)器
文件頁(yè)數(shù)： 29/61頁(yè)
文件大?。?/td> 2911K
代理商： TS68230CP10
The H3S status bit may be programmed for two in-
terpretations :
1. The H3S status bit is set when either the port
initial or final output latch can accept new data.
It is clear when both latches are full and cannot
accept new data.
2. The H3S status bit is set when both of the port
output latches are empty. It is clear when at
least one latch is full.
The programmable options of the H2 pin are :
1. H2 may be an edge-sensitive input pin inde-
pendent of H1 and the transfer of port data. On
the asserted edge of H2, the H2S status bit is
set. It is cleared by either the RESET pin being
asserted, writing a one to the particular status
bit in the port status register (PSR), or when the
H12 enable bit of the port general control re-
gister is clear.
2. H2 may be a general-purpose output pin that
is always negated. The H2S status bit is al-
ways clear.
3. H2 may be a general-purpose output pin that
is always asserted. The H2S status bit is al-
ways clear.
For pins used as inputs, data written to either data
register is double buffered and passed to the initial
or final output latch, as usual, but the output buffer
is disabled (refer to
3.3.2. Submode 01 - Pin-Defi-
nable Double-Buffered Output or Non-Latched
Input
).
Programmable Options Mode 1 - Port A Submode XX and Port B Submode X1
PACR
7 6
0 0
Port A Submode
Submode XX.
PACR
5 4 3
0 X X
1 X 0
1 X 1
H2 Control
Input pin - edge-sensitive status input, H2S is set on an asserted edge.
Output pin - negated, H2S is always cleared.
Output pin - asserted, H2S is always cleared.
PACR
2
0
1
H2 Interrupt Enable
The H2 interrupt is disabled.
The H2 interrupt is enabled.
PACR
1
0
1
H1 SVCRQ Enable
The H1 interrupt is disabled.
The H1 interrupt is enabled.
PACR
0
X
H1 Status Control
H1 is an edge-sensitive status input. H1S is set by an asserted edge of H1.
PBCR
7 6
0 0
Port B Submode
Submode X1.
TS68230
29/61
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