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參數(shù)資料
| 型號： | TS68230CP10 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | HMOS PARALLEL INTERFACE/TIMER |
| 中文描述： | HMO的并行接口/定時器 |
| 文件頁數(shù)： | 54/61頁 |
| 文件大?。?/td> | 2911K |
| 代理商： | TS68230CP10 |
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6.6. AC ELECTRICAL SPECIFICATIONS
(V
CC
= 5.0Vdc
±
5%, V
SS
= 0Vdc, T
A
= T
L
to T
H
unless otherwise noted)
Peripheral Output Timings
(figures 6.5)
8MHz
Min.
40
40
10MHz
Min.
40
40
Number
Parameter
Max.
Max.
Unit
16
17
18
19
Handshake Input H1(H4) Pulse Width Asserted
Handshake Input H1(H4) Pulse Width Negated
H1(H3) Asserted to H2(H4) Negated (delay time)
CLK Low to H2(H4) Asserted (delay time)
H2(H4) Asserted to H1(H3) Asserted
CLK Low to H2(H4) Pulse Negated (delay time)
Synchronized H1(H3) to CLK low on which DMAREQ is asserted
CLK
low
on
which
DMAREQ
is
asserted
to
CLK
low
on which
DMAREQ is negated
CLK Low to Port Output Data Valid (delay time) (modes 0 and 1)
Synchronized
H1(H3)
to
Port
Output
Data
Invalid
(modes
0
and 1)
H1 Negated to Port Output Data Valid (modes 2 and 3)
H1
Asserted
to
Port
Output
Data
High
Impedance
(modes
2
and
3)
H1(H3) Asserted to CLK High (setup time)
CLK Low to DMAREQ Low (delay time)
CLK Low to DMAREQ High (delay time)
ns
ns
ns
ns
ns
ns
150
100
120
100
20
(1)
21
(2)
22
(3.4)
23
0
0
125
3.5
3
125
3.5
3
2.5
2.5
2.5
2.5
CLK Per
CLK Per
24
150
2.5
70
70
120
2.5
50
70
ns
25
(3.4)
26
27
30
(5)
35
36
1.5
1.5
CLK Per
ns
ns
ns
ns
ns
0
0
50
0
0
40
0
0
120
120
100
100
2. This specification applies only when a pulsed handshake option is chosen and the pulse is not shortened due to an
early asserted edge of H1(H3).
3. The maximum value is caused by a peripheral access (H1(H3) asserted) and bus access (CS asserted) occurring
at the same time.
4. Syncrhonized means that the input signal has been seen by the PI/T on the appropriate edge of the clock (rising
edge for H1(H3) and falling edge for CS). (Refer to the
1.4 Bus Interface Operation
for the exception concerning
CS).
5. If the setup time on the rising edge of the clock is not met, H1(H3) may not be recognized until the next rising of
the clock.
TS68230
54/61
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| TS68230P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HMOS PARALLEL INTERFACE/TIMER |
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