- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373714 > TS68230CP10 (意法半導體) HMOS PARALLEL INTERFACE/TIMER PDF資料下載
參數(shù)資料
| 型號： | TS68230CP10 |
| 廠商： | 意法半導體 |
| 英文描述： | HMOS PARALLEL INTERFACE/TIMER |
| 中文描述： | HMO的并行接口/定時器 |
| 文件頁數(shù)： | 47/61頁 |
| 文件大?。?/td> | 2911K |
| 代理商： | TS68230CP10 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁當前第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁
5.2.4.2. External Clock.
7
6
This configuration allows measurement (counting)
of the number of input pulses occurring in an interval
in which the counter is enabled. The TIN input pin
provides the input pulses. Generally the TOUT and
TIACK pins are not used.
This configuration is similar to the elapsed time
measurement/system clock configuration except
that the TIN pin is used to provide the input frequen-
cy. It can be connected to a simple oscillator and the
same methods could be used. Alternately, it could
be gated off and on externally and the number of cy-
cles occurring while in the run state can be counted.
However, minimum pulse width high and low speci-
fications must be met.
5.2.5. DEVICE WATCHDOG.
7
6
5
4
This configuration provides the watchdog function
needed in many systems. The TIN pin is the timer
input whose period at the high (one) level is to be
checked. Once allowed by the processor, the TIN in-
put pin controls the run/halt mode. The TOUT pin is
connected to external circuitry requiring notification
when the TIN pin has been asserted longer than the
programmed time. The TIACK pin (timer interrupt
acknowledge) is only needed if the TOUT pin is
connected to the interrupt circuitry.
The processor loads the counter preload register
and timer control register, and then enables the ti-
mer. When the TIN input is asserted (one, high) the
timer transfers the contents of the counter preload
register to the counter and begins counting. If the
TIN input is negated before zero detect is reached,
the TOUT output and the ZDS status bit remain ne-
gated. If zero detect is reached while the TIN input
is still asserted, the ZDS status bit is set and the
TOUT output is asserted. (The counter rolls over
and keeps counting). In either case, when the TIN
input is negated the ZDS status bit is zero, the TOUT
output is negated, the counting stops, and the pres-
caler is forced to all ones (see figure 5.5).
5
4
3
2
1
0
Timer
Enable
TOUT/TIACK
Control
*
Z.D
Control
Clock
Control
0
0
X
1
0
1
X Changed
3
2
1
0
Timer
Enable
TOUT/TIACK
Control
*
Z.D
Control
Clock
Control
1
X
1
1
0
0
1 Changed
Figure 5.5 :
Device Watchdog Example.
TS68230
47/61
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TS68230CP8 | HMOS PARALLEL INTERFACE/TIMER |
| TS68230P | HMOS PARALLEL INTERFACE/TIMER |
| TS68230CFN8 | HMOS PARALLEL INTERFACE/TIMER |
| TS68302DESC01QYA | Integrated Multiprotocol Processor IMP |
| TS68302VA16 | Integrated Multiprotocol Processor IMP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TS68230CP8 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HMOS PARALLEL INTERFACE/TIMER |
| TS68230FN | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HMOS PARALLEL INTERFACE/TIMER |
| TS68230MC1B/C10 | 制造商:e2v technologies 功能描述: |
| TS68230MCB/C8 | 制造商:e2v technologies 功能描述: |
| TS68230P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HMOS PARALLEL INTERFACE/TIMER |
發(fā)布緊急采購，3分鐘左右您將得到回復。