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參數(shù)資料
| 型號： | TS68230CP10 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | HMOS PARALLEL INTERFACE/TIMER |
| 中文描述： | HMO的并行接口/定時器 |
| 文件頁數(shù)： | 34/61頁 |
| 文件大?。?/td> | 2911K |
| 代理商： | TS68230CP10 |
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3.6.2. DOUBLE-BUFFERED OUTPUT TRANS-
FERS. Data, written by the bus master to the PI/T,
is stored in the port’s output latch. The peripheral ac-
cepts the data by asserting H1, which causes the
next data to be moved to the port’s output latch as
soon as it is available. The H1S status bit, in the port
status register, may be programmed for two inter-
pretations. Normally the status bit is a one when
there is at least one latch in the double-buffered data
path that can accept new data. After writing one byte
of data to the ports, an interrupt service routine could
check this bit to determine if it could store another
byte ; thus filling both latches. When the bus master
is finished, it is often useful to be able to check whe-
ther all of the data has been transferred to the peri-
pheral. The H1S status control bit of the port A
control register provides this flexibility. The H1S sta-
tus bit is set when both output latches are empty.
The programmable options for H2 are :
1. H2 may be an output pin in the interlocked out-
put handshake protocol. It is asserted when
the port output latches are ready to transfer
new data. It is negated asynchronously follo-
wing the asserted edge of the H1 input. As
soon as the output latches become ready, H2
is again asserted. When the output double-
buffered latches are full, H2 remains asserted
until data is removed. Thus, anytime the H2
output is asserted, new output data may be
transferred by asserting H1. At other times
transitions on H1 are ignored. The H2S status
bit is always clear. When H12 enable in the
port general control register is clear, H2 is held
negated.
2. H2 may be an output pin in the pulsed output
handshake protocol. It is asserted exactly as in
the interlocked output protocol above, but never
remains asserted longer than four clock cycles.
Typically, a four clock pulse is generated. But
in the case that a subsequent H1 asserted edge
occurs before termination of the pulse, H2 is ne-
gated asynchronously shortening the pulse.
The H2S status bit is always zero. When H12
enable is zero, H2 is held negated.
Mode 3 can provide convenient high-speed 16-bit
transfers. The port A and B data registers are ad-
dressed for compatibility with the TS68000’s move
peripheral (MOVEP) instruction and with the 68440
DMAC. To take advantage of this port A should
contain the most significant data and always be read
or written by the bus master first. The interlocked
and pulsed handshake protocols, status bits, and
DMAREQ are keyed to the access of port B data re-
gister in mode 3. If it is accessed last, the 16-bit dou-
ble-buffered transfer proceeds smoothly.
The DMAREQ pin may be associatedwith either in-
put transfers (H3) or output transfers (H1), but not
both. Refer to table 3.5 for a summary of the port A
and B data paths in mode 3.
Table 3.5 :
Mode 3 Port A and B Data Paths
.
Mode
3
Read Port A and B Data Register
FIL, D. B.
Write Port A and B Data Register
IOL/FOL, D. B., Note 1
Note 1 : Data written to Port A goes to a temporary latch. When the Port B data register is later written, Port A
data is transferred to IOL/FOL.
Abbreviations :
IOL - Initial Output Latch
FOL - Final Output Latch
FIL - Final Input Latch
S. B. - Single Buffered
D. B. - Double Buffered
TS68230
34/61
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