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參數(shù)資料
| 型號： | TS8308500VGL |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, CBGA68 |
| 封裝： | 11 X 11 MM, 1.27MM PITCH, CERAMIC, BGA-68 |
| 文件頁數(shù)： | 20/50頁 |
| 文件大小： | 491K |
| 代理商： | TS8308500VGL |
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27
TS8308500
2193A–BDC–04/03
Single-ended ECL
Clock Input
In a single-ended configuration, enter at CLK (resp. CLKB) pin, with the inverted phase clock
input pin CLKB (respectively CLK) connected to -1.3V through the 50
termination resistor.
The in-phase input amplitude is 1V, centered on -1.3V common mode.
Figure 32. Single-ended Clock Input (ECL):
VCLK common mode = -1.3V; VCLKB = -1.3V
Noise Immunity
Information
Circuit noise immunity performance begins at design level.
Efforts have been made to the design to make it as insensitive as possible to chip environment
perturbations resulting from the circuit itself or induced by external circuitry. (Cascode stage
isolation, internal damping resistors, clamps, internal (on-chip) decoupling capacitors.)
Furthermore, the fully differential operation from the analog input up to the digital outputs pro-
vides enhanced noise immunity with common mode noise rejection.
Common mode noise voltage induced on the differential analog and clock inputs will be can-
celed out by these balanced differential amplifiers.
Moreover, proper active signal shielding has been provided on the chip to reduce the amount
of coupled noise on the active inputs.
The analog inputs and clock inputs of the TS8308500 device have been surrounded by ground
pins, which must be directly connected to the external ground plane.
Digital Outputs
The TS8308500 differential output buffers are internally loaded with 75
. The 75 resistors
are connected to the digital ground pins through a -0.8V level shift diode (see Figure 33, Fig-
ure 34, Figure 35 on page 29).
The TS8308500 output buffers are designed for driving 75
(default) or 50 properly termi-
nated impedance lines or coaxial cables. An 11 mA bias current flowing alternately into one of
the 75
resistors when switching ensures a 0.825V voltage drop across the resistor (untermi-
nated outputs).
The VPLUSD positive supply voltage allows the adjustment of the output common mode level
from -1.2V (VPLUSD = 0V for ECL output compatibility) to +1.2V (VPLUSD = 2.4V for LVDS output
compatibility).
Therefore, the single-ended output voltages vary approximately between -0.8V and -1.625V,
(outputs unterminated), around -1.2V common mode voltage.
-1.8V
-0.8V
t
[V]
VCLK
VCLKB = -1.3V
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