參數(shù)資料
型號: TS8308500VGL
廠商: E2V TECHNOLOGIES PLC
元件分類: ADC
英文描述: 1-CH 8-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, CBGA68
封裝: 11 X 11 MM, 1.27MM PITCH, CERAMIC, BGA-68
文件頁數(shù): 47/50頁
文件大小: 491K
代理商: TS8308500VGL
6
TS8308500
2193A–BDC–04/03
Gain error drift
Offset error drift
4
100
40
125
50
150
60
ppm/
°C
ppm/
°C
Transient Performance
Bit error rate
F
S = 500 Msps, FIN = 62.5 MHz
BER
4
1E-13
Error/
sample
(2)(4)
ADC settling time
V
IN -VINB = 400 mVpp
TS
4
0.5
1
ns
(2)
Overvoltage recovery time
TOR
4
0.5
1
ns
(2)
AC Performance
Single-ended or differential input and clock mode, 50% clock duty cycle (CLK, CLKB), binary output data format,
Tj = 70
°C, unless otherwise specified
Signal to noise and distortion ratio
SINAD
(2)
FS = 500 Msps, FIN = 20 MHz
4
43
45
dB
F
S = 500 Msps, FIN = 500 MHz
4
42
44
dB
F
S = 500 Msps, FIN = 1000 MHz (-1 dBFS)
4
38
40
dB
FS = 50 Msps, FIN = 25 MHz
1
43
46
dB
Effective number of bits
ENOB
F
S = 500 Msps, FIN = 20 MHz
4
7.0
7.2
Bits
FS = 500 Msps, FIN = 500 MHz
4
6.8
7.0
Bits
F
S = 500 Msps, FIN = 1000 MHz (-1 dBFS)
4
6.0
6.3
Bits
F
S = 50 Msps, FIN = 25 MHz
1
7.0
7.4
Bits
Signal to noise ratio
SNR
(2)
F
S = 500 Msps, FIN = 20 MHz
4
44
46
dB
F
S = 500 Msps, FIN = 500 MHz
4
44
45
dB
FS = 500 Msps, FIN = 1000 MHz (-1 dBFS)
4
40
43
dB
F
S = 50 Msps, FIN = 25 MHz
1
44
45
dB
Total harmonic distortion
|THD|
(2)
FS = 500 Msps, FIN = 20 MHz
450
53
dB
FS = 500 Msps, FIN = 500 MHz
4
48
50
dB
F
S = 500 Msps, FIN = 1000 MHz (-1 dBFS)
4
38
40
dB
F
S = 50 Msps, FIN = 25 MHz
1
44
54
dB
Table 3. Electrical Specifications (Continued)
Parameter
Symbol
Test
Level
Value
Unit
Note
Min
Typ
Max
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