參數(shù)資料
型號(hào)： TS8308500VGL
廠商： E2V TECHNOLOGIES PLC
元件分類： ADC
英文描述： 1-CH 8-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, CBGA68
封裝： 11 X 11 MM, 1.27MM PITCH, CERAMIC, BGA-68
文件頁(yè)數(shù)： 32/50頁(yè)
文件大?。?/td> 491K
代理商： TS8308500VGL
38
TS8308500
2193A–BDC–04/03
Notes:
1. GORB tied to VCC or floating: Binary output data format. GORB tied to GND: Gray output data format.
2. The common mode level of the output buffers is 1.2V below the positive digital supply.
For ECL compatibility the positive digital supply must be set at 0V (ground).
For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V.If the subsequent
LVDS circuitry can withstand a lower level for input common mode, it is remmended to lower the positive digital supply level
in the name proportion in order to spare power dissipation.
34
VIN
In-phase (+) analog input (double pad)
35
GND
Analog ground
36
V
INB
Inverted phase (-) analog input (double pad)
37
GND
Analog ground (double pad)
38
GAIN
ADC gain adjust input
39
V
CC
+5V supply (double pad)
40
VCC
+5V supply
41
OR
In-phase (+) Out of Range digital output
42
ORB
Inverted phase (-) Out of Range digital output
43
D7
In-phase (+) digital output, bit 7, Most Significant Bit
44
D7B
Inverted phase (-) digital output bit 7
45
D6
In-phase (+) digital output, bit 6
46
D6B
Inverted phase (-) digital output, bit 6
Table 7. TS8308500 Pad Description (Continued)
Pad number
Chip Pad Name
Chip Pad Function
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