參數(shù)資料
型號(hào): TS8308500VGL
廠商: E2V TECHNOLOGIES PLC
元件分類: ADC
英文描述: 1-CH 8-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, CBGA68
封裝: 11 X 11 MM, 1.27MM PITCH, CERAMIC, BGA-68
文件頁數(shù): 49/50頁
文件大小: 491K
代理商: TS8308500VGL
8
TS8308500
2193A–BDC–04/03
- Unterminated (source terminated) 75
controlled impedance lines: 100 ps/pF or 150 ps per additionnal ECLinPS termina-
tion load
10. Apply proper 50/75
impedance traces propagation time derating values: 6 ps/mm (155 ps/inch) for TSEV8308500GL Eval-
uation Board
11. Values for TOD and TDR track each other over temperature, (1% variation for TOD-TDR per 100
°C temperature variation).
Therefore TOD-TDR variation over temperature is negligible. Moreover, the internal (on-chip) and package skews between
each Data TODs and TDR effect can be considered negligible. Consequently, minimum values for TOD and TDR are never
more than 100 ps apart. The same is true for the TOD and TDR maximum values (see Advanced Application Notes about
“TOD-TDR Variation Over Temperature” on page 22).
12. Min value guarantees performance. Max value guarantees functionality
13. Min value guarantees functionality. Max value guarantees performance
14. Refer to product Application Notes
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