參數(shù)資料
型號(hào)： TS8308500VGL
廠商： E2V TECHNOLOGIES PLC
元件分類： ADC
英文描述： 1-CH 8-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, CBGA68
封裝： 11 X 11 MM, 1.27MM PITCH, CERAMIC, BGA-68
文件頁(yè)數(shù)： 42/50頁(yè)
文件大?。?/td> 491K
代理商： TS8308500VGL
47
TS8308500
2193A–BDC–04/03
(PSRR) Power Supply
Rejection Ratio
Ratio of input offset variation to a change in power supply voltage.
(SFDR) Spurious Free
Dynamic Range
Ratio expressed in dB of the RMS signal amplitude, set at 1 dB below full-scale, to the RMS
value of the next highest spectral component (peak spurious spectral component). SFDR is
the key parameter for selecting a converter to be used in a frequency domain application
(Radar systems, digital receiver, network analyzer, etc.). It may be reported in dBc (i.e.:
degrades as signal level is lowered), or in dBFS (i.e.: always related back to converter full
scale)
(SINAD) Signal to Noise
and Distortion Ratio
Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale, to the RMS
sum of all other spectral components, including the harmonics except DC.
(SNR) Signal to Noise
Ratio
Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale, to the RMS
sum of all other spectral components excluding the five first harmonics.
(TA) Aperture Delay
Delay between the rising edge of the differential clock inputs (CLK, CLKB) (zero crossing
point), and the time at which (VIN, VINB) is sampled.
(TC) Encoding Clock
Period
TC1 = Minimum clock pulse width (high) TC = TC1 + TC2
TC2 = Minimum clock pulse width (low)
(TD1) Time Delay from
Data to Data Ready
Time delay from Data transition to Data Ready.
(TD2) Time Delay from
Data Ready to Data
General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 = 1 encoding clock
period.
(TF) Fall Time
Time delay for the output Data signals to fall from 80% to 20% of delta between low level and
high level.
(THD) Total Harmonic
Distorsion
Ratio expressed in dBc of the RMS sum of the first five harmonic components, to the RMS
value of the measured fundamental spectral component.
(TOD) Digital Data
Output Delay
Delay from the falling edge of the differential clock inputs (CLK, CLKB) (zero crossing point) to
the next point of change in the differential output data (zero crossing) with a specified load.
(TPD) Pipeline Delay
Number of clock cycles between the sampling edge of an input data and the associated output
data being made available, (not taking in account the TOD). For the TS8388BF the TPD is 4
clock periods.
(TR) Rise Time
Time delay for the output Data signals to rise from 20% to 80% of delta between low level and
high level.
(TRDR) Data Ready
Reset Delay
Delay between the falling edge of the Data Ready output asynchronous Reset signal (DDRB)
and the reset to digital zero transition of the Data Ready output signal (DR).
(TS) Settling Time
Time delay to achieve 0.2% accuracy at the converter output when a 80% full-scale step func-
tion is applied to the differential analog input.
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