- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98293 > TS83102G0BMGS (ATMEL CORP) 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 PDF資料下載
參數(shù)資料
| 型號： | TS83102G0BMGS |
| 廠商： | ATMEL CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 |
| 封裝： | HERMATIC, CI-CGA-152 |
| 文件頁數(shù)： | 27/52頁 |
| 文件大?。?/td> | 1548K |
| 代理商： | TS83102G0BMGS |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當(dāng)前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
33
5360A–BDC–06/05
TS83102G0BMGS
JITTER
Aperture Uncertainty
The sample to sample variation in aperture delay. The voltage error due to jitter depends on
the slew rate of the signal at the sampling point
NPR
Noise Power Ratio
The NPR is measured to characterize the ADC’s performance in response to broad
bandwidth signals. When using a notch-filtered broadband white-noise generator as the
input to the ADC under test, the Noise-to-Power Ratio is defined as the ratio of the average
out-of-notch to the average in-notch power spectral density magnitudes for the FFT
spectrum of the ADC output sample test
NRZ
Non Return to Zero
When the input signal is larger than the upper bound of the ADC input range, the output code
is identical to the maximum code and the out-of-range bit is set to logic one. When the input
signal is smaller than the lower bound of the ADC input range, the output code is identical to
the minimum code, and the out-of-range bit is set to logic one (it is assumed that the input
signal amplitude remains within the absolute maximum ratings)
ORT
Overvoltage
Recovery Time
Time to recover 0.2% accuracy at the output, after a 150% full-scale step applied on the
input is reduced to midscale
PSRR
Power Supply
Rejection Ratio
PSRR is the ratio of input offset variation to a change in power supply voltage
SFDR
Spurious Free
Dynamic Range
The ratio expressed in dB of the RMS signal amplitude, set at 1 dB below full-scale, to the
RMS value of the next highest spectral component (peak spurious spectral component).
SFDR is the key parameter for selecting a converter to be used in a frequency domain
application (radar systems, digital receiver, network analyzer...). It may be reported in dBc
(i.e., degrades as signal level is lowered), or in dBFS (i.e. always related back to converter
full-scale)
SINAD
Signal to Noise and
Distortion Ratio
The ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale, to the
RMS sum of all other spectral components, including the harmonics except DC
SNR
Signal to Noise Ratio
The ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale, to the
RMS sum of all other spectral components excluding the first five harmonics
SSBW
Small Signal Input
Bandwidth
Analog input frequency at which the fundamental component in the digitally reconstructed
output waveform has fallen by 3 dB with respect to its low frequency value (determined by
FFT analysis) for input at full-scale -10 dB (-10 dBFS)
TA
Aperture Delay
The delay between the rising edge of the differential clock inputs (CLK,CLKB) (zero crossing
point), and the time at which (V
IN, VINB) is sampled
TC
Encoding Clock
Period
TC1 = minimum clock pulse width (high) TC = TC1 + TC2
TC2 = minimum clock pulse width (low)
TD1
Time Delay from Data
to Data Ready
General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 = 1 encoding clock
period
TD2
Time Delay from Data
Ready to Data
General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 = 1 encoding clock
period
TF
Fall Time
Time delay for the output data signals to fall from 80% to 20% of delta between low level and
high level
THD
Total Harmonic
Distortion
The ratio expressed in dBc of the RMS sum of the first five harmonic components, to the
RMS value of the measured fundamental spectral component
TOD
Digital Data
Output Delay
The delay from the falling edge of the differential clock inputs (CLK, CLKB) (zero crossing
point) to the next point of change in the differential output data (zero crossing) with a
specified load
TPD
Pipeline Delay
The number of clock cycles between the sampling edge of an input data and the associated
output data being made available (not taking in account the TOD). For the JTS8388B the
TPD is 4 clock periods
Table 8-1.
Definitions of Terms (Continued)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TS83102G0BVGL | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 |
| TS83102G0BCGL | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 |
| TS83110CZT | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDFP28 |
| TS83110MZT | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDFP28 |
| TS83110VZT | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDFP28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TS83102G0BVGL | 制造商:e2v technologies 功能描述:ADC SGL 2GSPS 10-BIT PARALLEL 152CBGA - Trays |
| TS83102G0CGL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog to Digital Converter |
| TS83102G0GSZR5 | 制造商:e2v technologies 功能描述:TS83102G0GSZR5 - Trays |
| TS831-3I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MICROPOWER VOLTAGE SUPERVISOR RESET ACTIVE LOW |
| TS831-3ID | 功能描述:監(jiān)控電路 2.71V Micropower AL RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。